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[RFC,10/11] drm/i915/preempt: Emit MI_ARB_CHECK before the start of user batch

Message ID 20170223191421.4502-6-michal.winiarski@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Michał Winiarski Feb. 23, 2017, 7:14 p.m. UTC
We should probably do this conditionally, based on whether preemption is
actually enabled.

Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Comments

Chris Wilson March 1, 2017, 12:53 p.m. UTC | #1
On Thu, Feb 23, 2017 at 08:14:20PM +0100, Michał Winiarski wrote:
> We should probably do this conditionally, based on whether preemption is
> actually enabled.
> 
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 869b96e..972f9bd 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1418,10 +1418,13 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
>  		req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
>  	}
>  
> -	cs = intel_ring_begin(req, 4);
> +	cs = intel_ring_begin(req, 6);
>  	if (IS_ERR(cs))
>  		return PTR_ERR(cs);
>  
> +	*cs++ = MI_ARB_CHECK;
> +	*cs++ = MI_NOOP;
> +
>  	/* FIXME(BDW): Address space and security selectors. */
>  	*cs++ = MI_BATCH_BUFFER_START_GEN8 | (ppgtt << 8) | (dispatch_flags &
>  		I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);

Shouldn't we only enable arbitration across the batch, i.e. add the
disable here? The flush and breadcrumb are not worth interrupting and
saves us some work if they are not.
-Chris
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 869b96e..972f9bd 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1418,10 +1418,13 @@  static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
 		req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
 	}
 
-	cs = intel_ring_begin(req, 4);
+	cs = intel_ring_begin(req, 6);
 	if (IS_ERR(cs))
 		return PTR_ERR(cs);
 
+	*cs++ = MI_ARB_CHECK;
+	*cs++ = MI_NOOP;
+
 	/* FIXME(BDW): Address space and security selectors. */
 	*cs++ = MI_BATCH_BUFFER_START_GEN8 | (ppgtt << 8) | (dispatch_flags &
 		I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);