From patchwork Thu Feb 23 19:44:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michel Thierry X-Patchwork-Id: 9588891 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 15040604A2 for ; Thu, 23 Feb 2017 19:44:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0190528773 for ; Thu, 23 Feb 2017 19:44:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E8861288BC; Thu, 23 Feb 2017 19:44:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8389428773 for ; Thu, 23 Feb 2017 19:44:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 595006EB21; Thu, 23 Feb 2017 19:44:23 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4B5076EB1F for ; Thu, 23 Feb 2017 19:44:22 +0000 (UTC) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Feb 2017 11:44:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.35,198,1484035200"; d="scan'208"; a="1134035319" Received: from relo-linux-11.sc.intel.com ([10.3.160.214]) by fmsmga002.fm.intel.com with ESMTP; 23 Feb 2017 11:44:21 -0800 From: Michel Thierry To: intel-gfx@lists.freedesktop.org Date: Thu, 23 Feb 2017 11:44:18 -0800 Message-Id: <20170223194421.28463-2-michel.thierry@intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170223194421.28463-1-michel.thierry@intel.com> References: <20170223194421.28463-1-michel.thierry@intel.com> Subject: [Intel-gfx] [RFC 2/3] drm/i915: Watchdog timeout: Ringbuffer command emission for gen8+ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Emit the required commands into the ring buffer for starting and stopping the watchdog timer before/after batch buffer start during batch buffer submission. Signed-off-by: Tomas Elf Signed-off-by: Ian Lister Signed-off-by: Arun Siluvery Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 26 +++++++++++ drivers/gpu/drm/i915/intel_lrc.c | 74 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_ringbuffer.h | 2 + 3 files changed, 102 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 35d2cb979452..348d81c40e81 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1416,8 +1416,15 @@ execbuf_submit(struct i915_execbuffer_params *params, u64 exec_start, exec_len; int instp_mode; u32 instp_mask, *cs; + bool watchdog_running = false; int ret; + /* + * NB: Place-holder until watchdog timeout is enabled through DRM + * interface + */ + bool enable_watchdog = false; + ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas); if (ret) return ret; @@ -1480,6 +1487,18 @@ execbuf_submit(struct i915_execbuffer_params *params, return ret; } + /* Start watchdog timer */ + if (enable_watchdog) { + if (!params->engine->emit_start_watchdog) + return -EINVAL; + + ret = params->engine->emit_start_watchdog(params->request); + if (ret) + return ret; + + watchdog_running = true; + } + exec_len = args->batch_len; exec_start = params->batch->node.start + params->args_batch_start_offset; @@ -1493,6 +1512,13 @@ execbuf_submit(struct i915_execbuffer_params *params, if (ret) return ret; + /* Cancel watchdog timer */ + if (watchdog_running && params->engine->emit_stop_watchdog) { + ret = params->engine->emit_stop_watchdog(params->request); + if (ret) + return ret; + } + i915_gem_execbuffer_move_to_active(vmas, params->request); return 0; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 8c9ebf0cebf7..b4939d9f338a 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1474,6 +1474,72 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request, return 0; } +static int gen8_emit_start_watchdog(struct drm_i915_gem_request *req) +{ + struct intel_engine_cs *engine = req->engine; + struct i915_gem_context *ctx = req->ctx; + u32 *cs; + + cs = intel_ring_begin(req, 8); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + /* + * watchdog register must never be programmed to zero. This would + * cause the watchdog counter to exceed and not allow the engine to + * go into IDLE state + */ + GEM_BUG_ON(ctx->watchdog_threshold == 0); + + /* Set counter period */ + *cs++ = MI_LOAD_REGISTER_IMM(1); + *cs++ = i915_mmio_reg_offset(RING_THRESH(engine->mmio_base)); + *cs++ = ctx->watchdog_threshold; + *cs++ = MI_NOOP; + + /* Start counter */ + *cs++ = MI_LOAD_REGISTER_IMM(1); + *cs++ = i915_mmio_reg_offset(RING_CNTR(engine->mmio_base)); + *cs++ = GEN8_WATCHDOG_ENABLE; + *cs++ = MI_NOOP; + intel_ring_advance(req, cs); + + return 0; +} + +static int gen8_emit_stop_watchdog(struct drm_i915_gem_request *req) +{ + struct intel_engine_cs *engine = req->engine; + u32 *cs; + + cs = intel_ring_begin(req, 4); + if (IS_ERR(cs)) + return PTR_ERR(cs); + + *cs++ = MI_LOAD_REGISTER_IMM(1); + *cs++ = i915_mmio_reg_offset(RING_CNTR(engine->mmio_base)); + + switch (engine->id) { + default: + WARN(1, "%s does not support watchdog timeout!\n", + engine->name); + /* default to render engine */ + case RCS: + *cs++ = GEN8_RCS_WATCHDOG_DISABLE; + break; + case VCS: + case VCS2: + case VECS: + *cs++ = GEN8_XCS_WATCHDOG_DISABLE; + break; + } + + *cs++ = MI_NOOP; + intel_ring_advance(req, cs); + + return 0; +} + /* * Reserve space for 2 NOOPs at the end of each request to be * used as a workaround for not being allowed to do lite @@ -1740,6 +1806,8 @@ int logical_render_ring_init(struct intel_engine_cs *engine) engine->emit_flush = gen8_emit_flush_render; engine->emit_breadcrumb = gen8_emit_breadcrumb_render; engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz; + engine->emit_start_watchdog = gen8_emit_start_watchdog; + engine->emit_stop_watchdog = gen8_emit_stop_watchdog; ret = intel_engine_create_scratch(engine, PAGE_SIZE); if (ret) @@ -1763,6 +1831,12 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine) { logical_ring_setup(engine); + /* BCS engine does not have a watchdog-expired irq */ + if (engine->id != BCS) { + engine->emit_start_watchdog = gen8_emit_start_watchdog; + engine->emit_stop_watchdog = gen8_emit_stop_watchdog; + } + return logical_ring_init(engine); } diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 0f29e07a9581..5a9764708186 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -282,6 +282,8 @@ struct intel_engine_cs { int (*emit_flush)(struct drm_i915_gem_request *request, u32 mode); + int (*emit_start_watchdog)(struct drm_i915_gem_request *req); + int (*emit_stop_watchdog)(struct drm_i915_gem_request *req); #define EMIT_INVALIDATE BIT(0) #define EMIT_FLUSH BIT(1) #define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH)