diff mbox

drm/i915: Pass pipe_config to pch_enable() functions

Message ID 20170302094327.8301-1-ander.conselvan.de.oliveira@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ander Conselvan de Oliveira March 2, 2017, 9:43 a.m. UTC 
Using crtc->config directly is being removed in favor of passing a
pipe_config. Follow the trend and pass pipe_config to pch_enable()
functions.

v2: s/pipe_config/crtc_state/ (Ville)
  - constify crtc_state. (Ville)
  - take crtc from crtc_state. (Ville)
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

Comments

Ville Syrjala March 2, 2017, 10:07 a.m. UTC | #1 
On Thu, Mar 02, 2017 at 11:43:27AM +0200, Ander Conselvan de Oliveira wrote:
> Using crtc->config directly is being removed in favor of passing a
> pipe_config. Follow the trend and pass pipe_config to pch_enable()
> functions.
> 
> v2: s/pipe_config/crtc_state/ (Ville)
>   - constify crtc_state. (Ville)
>   - take crtc from crtc_state. (Ville)

Neat. The other patches in the series could also benefit from these
tricks. I'd like to at least see the consts sprinkled around to make
people think twice before they touch the state in the wrong place.
The other changes are optional.

With the consts, patches 2-7 are also 
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++--------
>  1 file changed, 10 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index bfb99c6..9dc6a1b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4456,8 +4456,9 @@ intel_trans_dp_port_sel(struct intel_crtc *crtc)
>   *   - DP transcoding bits
>   *   - transcoder
>   */
> -static void ironlake_pch_enable(struct intel_crtc *crtc)
> +static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
>  {
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	int pipe = crtc->pipe;
> @@ -4484,7 +4485,7 @@ static void ironlake_pch_enable(struct intel_crtc *crtc)
>  		temp = I915_READ(PCH_DPLL_SEL);
>  		temp |= TRANS_DPLL_ENABLE(pipe);
>  		sel = TRANS_DPLLB_SEL(pipe);
> -		if (crtc->config->shared_dpll ==
> +		if (crtc_state->shared_dpll ==
>  		    intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
>  			temp |= sel;
>  		else
> @@ -4509,9 +4510,9 @@ static void ironlake_pch_enable(struct intel_crtc *crtc)
>  
>  	/* For PCH DP, enable TRANS_DP_CTL */
>  	if (HAS_PCH_CPT(dev_priv) &&
> -	    intel_crtc_has_dp_encoder(crtc->config)) {
> +	    intel_crtc_has_dp_encoder(crtc_state)) {
>  		const struct drm_display_mode *adjusted_mode =
> -			&crtc->config->base.adjusted_mode;
> +			&crtc_state->base.adjusted_mode;
>  		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
>  		i915_reg_t reg = TRANS_DP_CTL(pipe);
>  		temp = I915_READ(reg);
> @@ -4546,10 +4547,11 @@ static void ironlake_pch_enable(struct intel_crtc *crtc)
>  	ironlake_enable_pch_transcoder(dev_priv, pipe);
>  }
>  
> -static void lpt_pch_enable(struct intel_crtc *crtc)
> +static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
>  {
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  
>  	assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
>  
> @@ -5283,7 +5285,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
>  	intel_enable_pipe(intel_crtc);
>  
>  	if (intel_crtc->config->has_pch_encoder)
> -		ironlake_pch_enable(intel_crtc);
> +		ironlake_pch_enable(pipe_config);
>  
>  	assert_vblank_disabled(crtc);
>  	drm_crtc_vblank_on(crtc);
> @@ -5393,7 +5395,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>  		intel_enable_pipe(intel_crtc);
>  
>  	if (intel_crtc->config->has_pch_encoder)
> -		lpt_pch_enable(intel_crtc);
> +		lpt_pch_enable(pipe_config);
>  
>  	if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
>  		intel_ddi_set_vc_payload_alloc(crtc, true);
> -- 
> 2.9.3
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bfb99c6..9dc6a1b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4456,8 +4456,9 @@  intel_trans_dp_port_sel(struct intel_crtc *crtc)
  *   - DP transcoding bits
  *   - transcoder
  */
-static void ironlake_pch_enable(struct intel_crtc *crtc)
+static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int pipe = crtc->pipe;
@@ -4484,7 +4485,7 @@  static void ironlake_pch_enable(struct intel_crtc *crtc)
 		temp = I915_READ(PCH_DPLL_SEL);
 		temp |= TRANS_DPLL_ENABLE(pipe);
 		sel = TRANS_DPLLB_SEL(pipe);
-		if (crtc->config->shared_dpll ==
+		if (crtc_state->shared_dpll ==
 		    intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
 			temp |= sel;
 		else
@@ -4509,9 +4510,9 @@  static void ironlake_pch_enable(struct intel_crtc *crtc)
 
 	/* For PCH DP, enable TRANS_DP_CTL */
 	if (HAS_PCH_CPT(dev_priv) &&
-	    intel_crtc_has_dp_encoder(crtc->config)) {
+	    intel_crtc_has_dp_encoder(crtc_state)) {
 		const struct drm_display_mode *adjusted_mode =
-			&crtc->config->base.adjusted_mode;
+			&crtc_state->base.adjusted_mode;
 		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
 		i915_reg_t reg = TRANS_DP_CTL(pipe);
 		temp = I915_READ(reg);
@@ -4546,10 +4547,11 @@  static void ironlake_pch_enable(struct intel_crtc *crtc)
 	ironlake_enable_pch_transcoder(dev_priv, pipe);
 }
 
-static void lpt_pch_enable(struct intel_crtc *crtc)
+static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 	assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
 
@@ -5283,7 +5285,7 @@  static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
 	intel_enable_pipe(intel_crtc);
 
 	if (intel_crtc->config->has_pch_encoder)
-		ironlake_pch_enable(intel_crtc);
+		ironlake_pch_enable(pipe_config);
 
 	assert_vblank_disabled(crtc);
 	drm_crtc_vblank_on(crtc);
@@ -5393,7 +5395,7 @@  static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 		intel_enable_pipe(intel_crtc);
 
 	if (intel_crtc->config->has_pch_encoder)
-		lpt_pch_enable(intel_crtc);
+		lpt_pch_enable(pipe_config);
 
 	if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
 		intel_ddi_set_vc_payload_alloc(crtc, true);