From patchwork Mon Mar 6 23:54:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 9607865 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F3241601D2 for ; Mon, 6 Mar 2017 23:54:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DAF3928490 for ; Mon, 6 Mar 2017 23:54:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CF46E28499; Mon, 6 Mar 2017 23:54:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9203B28490 for ; Mon, 6 Mar 2017 23:54:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6A8BF6E591; Mon, 6 Mar 2017 23:54:29 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id AD3CD6E58A for ; Mon, 6 Mar 2017 23:54:28 +0000 (UTC) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga105.fm.intel.com with ESMTP; 06 Mar 2017 15:54:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,256,1484035200"; d="scan'208";a="233013110" Received: from abahri-mobl.ger.corp.intel.com (HELO mwahaha.ger.corp.intel.com) ([10.252.2.118]) by fmsmga004.fm.intel.com with ESMTP; 06 Mar 2017 15:54:27 -0800 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Date: Mon, 6 Mar 2017 23:54:10 +0000 Message-Id: <20170306235414.23407-12-matthew.auld@intel.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170306235414.23407-1-matthew.auld@intel.com> References: <20170306235414.23407-1-matthew.auld@intel.com> Subject: [Intel-gfx] [PATCH 11/15] drm/i915: support inserting 64K pages in the ppgtt X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_gtt.c | 70 +++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 0fb67941ba6b..4d863de6473d 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -848,6 +848,73 @@ static __always_inline struct gen8_insert_pte gen8_insert_pte(u64 start) } static __always_inline bool +gen8_ppgtt_insert_64K_pte_entries(struct i915_hw_ppgtt *ppgtt, + struct i915_page_directory_pointer *pdp, + struct sgt_dma *iter, + struct gen8_insert_pte *idx, + enum i915_cache_level cache_level) +{ + struct i915_page_directory *pd; + const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level); + gen8_pte_t *vaddr; + bool ret; + + GEM_BUG_ON(idx->pte % 16); + GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->base)); + /* TODO: probably move this to the allocation phase.. */ + pd = pdp->page_directory[idx->pdpe]; + vaddr = kmap_atomic_px(pd); + vaddr[idx->pde] |= GEN8_PDE_IPS_64K; + kunmap_atomic(vaddr); + + vaddr = kmap_atomic_px(pd->page_table[idx->pde]); + do { + vaddr[idx->pte] = pte_encode | iter->dma; + iter->dma += I915_GTT_PAGE_SIZE_64K; + if (iter->dma >= iter->max) { + iter->sg = __sg_next(iter->sg); + if (!iter->sg) { + ret = false; + break; + } + + iter->dma = sg_dma_address(iter->sg); + iter->max = iter->dma + iter->sg->length; + } + + idx->pte += 16; + + if (idx->pte == GEN8_PTES) { + idx->pte = 0; + + if (++idx->pde == I915_PDES) { + idx->pde = 0; + + /* Limited by sg length for 3lvl */ + if (++idx->pdpe == GEN8_PML4ES_PER_PML4) { + idx->pdpe = 0; + ret = true; + break; + } + + GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->base)); + pd = pdp->page_directory[idx->pdpe]; + } + + kunmap_atomic(vaddr); + vaddr = kmap_atomic_px(pd); + vaddr[idx->pde] |= GEN8_PDE_IPS_64K; + kunmap_atomic(vaddr); + + vaddr = kmap_atomic_px(pd->page_table[idx->pde]); + } + } while (1); + kunmap_atomic(vaddr); + + return ret; +} + +static __always_inline bool gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt, struct i915_page_directory_pointer *pdp, struct sgt_dma *iter, @@ -947,6 +1014,9 @@ static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm, case I915_GTT_PAGE_SIZE: insert_entries = gen8_ppgtt_insert_pte_entries; break; + case I915_GTT_PAGE_SIZE_64K: + insert_entries = gen8_ppgtt_insert_64K_pte_entries; + break; default: MISSING_CASE(page_size); return;