From patchwork Fri Mar 10 02:22:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhenyu Wang X-Patchwork-Id: 9614511 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 11B6B602B4 for ; Fri, 10 Mar 2017 02:25:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EE623286E5 for ; Fri, 10 Mar 2017 02:25:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DFEE1286F1; Fri, 10 Mar 2017 02:25:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 61FA4286E5 for ; Fri, 10 Mar 2017 02:25:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E23986E0A5; Fri, 10 Mar 2017 02:25:00 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 985E66E090; Fri, 10 Mar 2017 02:24:59 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Mar 2017 18:24:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,138,1486454400"; d="scan'208,223";a="832980520" Received: from debian-nuc.sh.intel.com ([10.239.13.21]) by FMSMGA003.fm.intel.com with ESMTP; 09 Mar 2017 18:24:57 -0800 From: Zhenyu Wang To: intel-gfx@lists.freedesktop.org Date: Fri, 10 Mar 2017 10:22:38 +0800 Message-Id: <20170310022238.3191-1-zhenyuw@linux.intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170309102537.1826-1-zhenyuw@linux.intel.com> References: <20170309102537.1826-1-zhenyuw@linux.intel.com> Cc: Terrence Xu , intel-gvt-dev@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v2] drm/i915: Fix vGPU balloon for ggtt guard page X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From commit a6508ded2a66 ("drm/i915: Use page coloring to provide the guard page at the end of the GTT"), we no longer explicitly subtract guard page at end for GGTT address space init, so shouldn't subtract that for vGPU balloon too, as that will leave that end page to be available for vGPU. Change balloon to cover full range too. This fixes to use recent drm-intel tip kernel for guest OS. Found by GVT-g cmd parser that guest kernel uses end page as scratch then try to run MI_STORE_REG_MEM onto it. v2: remove old comments Cc: Terrence Xu Signed-off-by: Zhenyu Wang Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/i915_vgpu.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c index 14014068dfcf..4ab8a973b61f 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.c +++ b/drivers/gpu/drm/i915/i915_vgpu.c @@ -218,13 +218,9 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv) goto err; } - /* - * No need to partition out the last physical page, - * because it is reserved to the guard page. - */ - if (unmappable_end < ggtt_end - PAGE_SIZE) { + if (unmappable_end < ggtt_end) { ret = vgt_balloon_space(ggtt, &bl_info.space[3], - unmappable_end, ggtt_end - PAGE_SIZE); + unmappable_end, ggtt_end); if (ret) goto err; }