From patchwork Tue Mar 28 18:00:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Micha=C5=82_Winiarski?= X-Patchwork-Id: 9650319 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B0FE4601D7 for ; Tue, 28 Mar 2017 18:01:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B93AA2845F for ; Tue, 28 Mar 2017 18:01:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AE32C28464; Tue, 28 Mar 2017 18:01:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.6 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RCVD_IN_SORBS_SPAM,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2A2C828469 for ; Tue, 28 Mar 2017 18:01:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B57666E64E; Tue, 28 Mar 2017 18:01:39 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 12E406E64E for ; Tue, 28 Mar 2017 18:01:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490724099; x=1522260099; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bNpqe1AO1JphPYCDBFm1zjMR9joBDDcK4MIoxXa2ROE=; b=PjrsACBlCjWyxFRSXAr6toMkQItKj9+m7O1E9H5sfRyAcp1SKV4t0t9L zo3RJn8/YMGfJCwXh798H0SL3eLSmw==; Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Mar 2017 11:01:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.36,237,1486454400"; d="scan'208"; a="1148045219" Received: from irsmsx102.ger.corp.intel.com ([163.33.3.155]) by fmsmga002.fm.intel.com with ESMTP; 28 Mar 2017 11:01:37 -0700 Received: from mwiniars-main.igk.intel.com (172.28.171.152) by IRSMSX102.ger.corp.intel.com (163.33.3.155) with Microsoft SMTP Server id 14.3.319.2; Tue, 28 Mar 2017 19:01:36 +0100 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= To: Date: Tue, 28 Mar 2017 20:00:28 +0200 Message-ID: <20170328180029.1073-3-michal.winiarski@intel.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170328180029.1073-1-michal.winiarski@intel.com> References: <20170328180029.1073-1-michal.winiarski@intel.com> MIME-Version: 1.0 X-Originating-IP: [172.28.171.152] Subject: [Intel-gfx] [RFC 3/4] drm/i915/scheduler: Use priorities when resubmitting after reset X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Now that we're able to unsubmit requests, we can take advantage of it during reset. Rather than resubmitting the previous workload directly to GuC/ELSP, we can simply move the requests back to priority queue, submitting from the tasklet instead. Cc: Chris Wilson Cc: Michel Thierry Cc: Mika Kuoppala Signed-off-by: Michał Winiarski --- drivers/gpu/drm/i915/i915_gem.c | 1 + drivers/gpu/drm/i915/i915_guc_submission.c | 12 --- drivers/gpu/drm/i915/intel_lrc.c | 127 ++++++++++++++++------------- 3 files changed, 71 insertions(+), 69 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 84ea249..747ff37 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2924,6 +2924,7 @@ void i915_gem_reset_finish(struct drm_i915_private *dev_priv) for_each_engine(engine, dev_priv, id) { tasklet_enable(&engine->irq_tasklet); kthread_unpark(engine->breadcrumbs.signaler); + tasklet_hi_schedule(&engine->irq_tasklet); } } diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index 082f8ae..9975244 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -1245,24 +1245,12 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv) guc_interrupts_capture(dev_priv); for_each_engine(engine, dev_priv, id) { - const int wqi_size = sizeof(struct guc_wq_item); - struct drm_i915_gem_request *rq; - /* The tasklet was initialised by execlists, and may be in * a state of flux (across a reset) and so we just want to * take over the callback without changing any other state * in the tasklet. */ engine->irq_tasklet.func = i915_guc_irq_handler; - clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); - - /* Replay the current set of previously submitted requests */ - spin_lock_irq(&engine->timeline->lock); - list_for_each_entry(rq, &engine->timeline->requests, link) { - guc_client_update_wq_rsvd(client, wqi_size); - __i915_guc_submit(rq); - } - spin_unlock_irq(&engine->timeline->lock); } return 0; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 107cf91..ff34aba 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -377,6 +377,22 @@ static void execlists_submit_ports(struct intel_engine_cs *engine) writel(lower_32_bits(desc[0]), elsp); } +static void execlists_clear_ports(struct intel_engine_cs *engine) +{ + struct execlist_port *port = engine->execlist_port; + struct drm_i915_gem_request *rq; + + rq = port->request; + while (rq) { + i915_gem_request_put(rq); + memset(port, 0, sizeof(*port)); + if (port != engine->execlist_port) + break; + port++; + rq = port->request; + } +} + static bool ctx_single_port_submission(const struct i915_gem_context *ctx) { return (IS_ENABLED(CONFIG_DRM_I915_GVT) && @@ -504,11 +520,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine) execlists_submit_ports(engine); } -static bool execlists_elsp_idle(struct intel_engine_cs *engine) -{ - return !engine->execlist_port[0].request; -} - static bool execlists_elsp_ready(const struct intel_engine_cs *engine) { const struct execlist_port *port = engine->execlist_port; @@ -895,6 +906,25 @@ static int execlists_request_alloc(struct drm_i915_gem_request *request) return ret; } +static void intel_lr_resubmit_requests(struct intel_engine_cs *engine) +{ + struct drm_i915_gem_request *rq, *prev; + + lockdep_assert_held(&engine->timeline->lock); + + list_for_each_entry_safe_reverse(rq, prev, + &engine->timeline->requests, link) { + if (!i915_gem_request_completed(rq)) { + __i915_gem_request_unsubmit(rq); + trace_i915_gem_request_out(rq); + if (insert_request(&rq->priotree, + &engine->execlist_queue, true)) + engine->execlist_first = &rq->priotree.node; + } else + break; + } +} + /* * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after * PIPE_CONTROL instruction. This is required for the flush to happen correctly @@ -1160,11 +1190,6 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine) return ret; } -static u32 port_seqno(struct execlist_port *port) -{ - return port->request ? port->request->global_seqno : 0; -} - static int gen8_init_common_ring(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; @@ -1186,18 +1211,6 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine) DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); - /* After a GPU reset, we may have requests to replay */ - clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); - if (!i915.enable_guc_submission && !execlists_elsp_idle(engine)) { - DRM_DEBUG_DRIVER("Restarting %s from requests [0x%x, 0x%x]\n", - engine->name, - port_seqno(&engine->execlist_port[0]), - port_seqno(&engine->execlist_port[1])); - engine->execlist_port[0].count = 0; - engine->execlist_port[1].count = 0; - execlists_submit_ports(engine); - } - return 0; } @@ -1237,10 +1250,10 @@ static int gen9_init_render_ring(struct intel_engine_cs *engine) static void reset_common_ring(struct intel_engine_cs *engine, struct drm_i915_gem_request *request) { - struct execlist_port *port = engine->execlist_port; struct intel_context *ce; + unsigned long flags; - /* If the request was innocent, we leave the request in the ELSP + /* If the request was innocent, we leave the request intact * and will try to replay it on restarting. The context image may * have been corrupted by the reset, in which case we may have * to service a new GPU hang, but more likely we can continue on @@ -1250,42 +1263,42 @@ static void reset_common_ring(struct intel_engine_cs *engine, * and have to at least restore the RING register in the context * image back to the expected values to skip over the guilty request. */ - if (!request || request->fence.error != -EIO) - return; - - /* We want a simple context + ring to execute the breadcrumb update. - * We cannot rely on the context being intact across the GPU hang, - * so clear it and rebuild just what we need for the breadcrumb. - * All pending requests for this context will be zapped, and any - * future request will be after userspace has had the opportunity - * to recreate its own state. - */ - ce = &request->ctx->engine[engine->id]; - execlists_init_reg_state(ce->lrc_reg_state, - request->ctx, engine, ce->ring); - - /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */ - ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = - i915_ggtt_offset(ce->ring->vma); - ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix; - - request->ring->head = request->postfix; - intel_ring_update_space(request->ring); - - /* Catch up with any missed context-switch interrupts */ - if (request->ctx != port[0].request->ctx) { - i915_gem_request_put(port[0].request); - port[0] = port[1]; - memset(&port[1], 0, sizeof(port[1])); + if (request && request->fence.error == -EIO) { + /* We want a simple context + ring to execute the breadcrumb + * update. We cannot rely on the context being intact across + * the GPU hang, so clear it and rebuild just what we need for + * the breadcrumb. All pending requests for this context will + * be zapped, and any future request will be after userspace + * has had the opportunity to recreate its own state. + */ + ce = &request->ctx->engine[engine->id]; + execlists_init_reg_state(ce->lrc_reg_state, + request->ctx, engine, ce->ring); + + + /* Move the RING_HEAD onto the breadcrumb, + * past the hanging batch */ + ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = + i915_ggtt_offset(ce->ring->vma); + ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix; + + request->ring->head = request->postfix; + intel_ring_update_space(request->ring); + + /* Reset WaIdleLiteRestore:bdw,skl as well */ + request->tail = + intel_ring_wrap(request->ring, + request->wa_tail - + WA_TAIL_DWORDS * sizeof(u32)); + assert_ring_tail_valid(request->ring, request->tail); } - GEM_BUG_ON(request->ctx != port[0].request->ctx); + spin_lock_irqsave(&engine->timeline->lock, flags); + intel_lr_resubmit_requests(engine); + spin_unlock_irqrestore(&engine->timeline->lock, flags); - /* Reset WaIdleLiteRestore:bdw,skl as well */ - request->tail = - intel_ring_wrap(request->ring, - request->wa_tail - WA_TAIL_DWORDS*sizeof(u32)); - assert_ring_tail_valid(request->ring, request->tail); + execlists_clear_ports(engine); + clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); } static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)