From patchwork Tue Apr 4 22:11:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 9662675 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 813456032D for ; Tue, 4 Apr 2017 22:11:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 736F222B39 for ; Tue, 4 Apr 2017 22:11:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 685AA28587; Tue, 4 Apr 2017 22:11:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2C63A22B39 for ; Tue, 4 Apr 2017 22:11:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 53AB56E6ED; Tue, 4 Apr 2017 22:11:43 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 39AC16E6EC for ; Tue, 4 Apr 2017 22:11:42 +0000 (UTC) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP; 04 Apr 2017 15:11:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,276,1486454400"; d="scan'208";a="83060596" Received: from cmachale-mobl1.ger.corp.intel.com (HELO mwahaha.ger.corp.intel.com) ([10.252.25.9]) by orsmga005.jf.intel.com with ESMTP; 04 Apr 2017 15:11:41 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Date: Tue, 4 Apr 2017 23:11:21 +0100 Message-Id: <20170404221128.3943-12-matthew.auld@intel.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170404221128.3943-1-matthew.auld@intel.com> References: <20170404221128.3943-1-matthew.auld@intel.com> Subject: [Intel-gfx] [PATCH 11/18] drm/i915: support inserting 1G pages in the ppgtt X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_gtt.c | 45 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_gem_gtt.h | 2 ++ 2 files changed, 47 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 9dc12955f557..5269092ba048 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -848,6 +848,48 @@ static __always_inline struct gen8_insert_pte gen8_insert_pte(u64 start) } static __always_inline bool +gen8_ppgtt_insert_1G_pdpe_entries(struct i915_hw_ppgtt *ppgtt, + struct i915_page_directory_pointer *pdp, + struct sgt_dma *iter, + struct gen8_insert_pte *idx, + enum i915_cache_level cache_level) +{ + const gen8_pte_t pdpe_encode = gen8_pte_encode(GEN8_PDPE_PS_1G, + cache_level); + gen8_pte_t *vaddr; + bool ret; + + GEM_BUG_ON(idx->pte); + GEM_BUG_ON(idx->pde); + GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->base)); + vaddr = kmap_atomic_px(pdp); + do { + vaddr[idx->pdpe] = pdpe_encode | iter->dma; + iter->dma += I915_GTT_PAGE_SIZE_1G; + if (iter->dma >= iter->max) { + iter->sg = __sg_next(iter->sg); + if (!iter->sg) { + ret = false; + break; + } + + iter->dma = sg_dma_address(iter->sg); + iter->max = iter->dma + iter->sg->length; + } + + if (++idx->pdpe == GEN8_PML4ES_PER_PML4) { + idx->pdpe = 0; + ret = true; + break; + } + + } while (1); + kunmap_atomic(vaddr); + + return ret; +} + +static __always_inline bool gen8_ppgtt_insert_2M_pde_entries(struct i915_hw_ppgtt *ppgtt, struct i915_page_directory_pointer *pdp, struct sgt_dma *iter, @@ -1071,6 +1113,9 @@ static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm, case I915_GTT_PAGE_SIZE_2M: insert_entries = gen8_ppgtt_insert_2M_pde_entries; break; + case I915_GTT_PAGE_SIZE_1G: + insert_entries = gen8_ppgtt_insert_1G_pdpe_entries; + break; default: MISSING_CASE(page_size); return; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index cfe31db6b400..8b970e9e764c 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -161,6 +161,8 @@ typedef u64 gen8_ppgtt_pml4e_t; #define GEN8_PDE_IPS_64K BIT(11) #define GEN8_PDE_PS_2M BIT(7) +#define GEN8_PDPE_PS_1G BIT(7) + struct sg_table; struct intel_rotation_info {