From patchwork Tue Apr 4 22:11:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 9662665 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1A0786032D for ; Tue, 4 Apr 2017 22:11:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0BE8822B39 for ; Tue, 4 Apr 2017 22:11:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 00D0B28583; Tue, 4 Apr 2017 22:11:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AD8FB22B39 for ; Tue, 4 Apr 2017 22:11:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3E7D96E6DF; Tue, 4 Apr 2017 22:11:39 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2D7946E6DF for ; Tue, 4 Apr 2017 22:11:38 +0000 (UTC) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP; 04 Apr 2017 15:11:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,276,1486454400"; d="scan'208";a="83060581" Received: from cmachale-mobl1.ger.corp.intel.com (HELO mwahaha.ger.corp.intel.com) ([10.252.25.9]) by orsmga005.jf.intel.com with ESMTP; 04 Apr 2017 15:11:37 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Date: Tue, 4 Apr 2017 23:11:17 +0100 Message-Id: <20170404221128.3943-8-matthew.auld@intel.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170404221128.3943-1-matthew.auld@intel.com> References: <20170404221128.3943-1-matthew.auld@intel.com> Subject: [Intel-gfx] [PATCH 07/18] drm/i915: introduce ppgtt page coloring X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP To enable 64K pages we need to set the intermediate-page-size(IPS) bit of the pde, therefore a page table is said to be either operating in 64K or 4K mode. To accommodate this vm placement restriction we introduce a color for pages and corresponding color_adjust callback. Signed-off-by: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_gtt.c | 25 +++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_gem_gtt.h | 6 ++++++ drivers/gpu/drm/i915/i915_vma.c | 2 ++ 3 files changed, 33 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 0989af4a17e4..ddc3db345b76 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1332,6 +1332,28 @@ static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt *ppgtt) return -ENOMEM; } +static void i915_page_color_adjust(const struct drm_mm_node *node, + unsigned long color, + u64 *start, + u64 *end) +{ + GEM_BUG_ON(!is_valid_gtt_page_size(color)); + + if (!(color & (I915_GTT_PAGE_SIZE_4K | I915_GTT_PAGE_SIZE_64K))) + return; + + GEM_BUG_ON(node->allocated && !is_valid_gtt_page_size(node->color)); + + if (i915_node_color_differs(node, color)) + *start = roundup(*start, 1 << GEN8_PDE_SHIFT); + + node = list_next_entry(node, node_list); + if (i915_node_color_differs(node, color)) + *end = rounddown(*end, 1 << GEN8_PDE_SHIFT); + + GEM_BUG_ON(node->allocated && !is_valid_gtt_page_size(node->color)); +} + /* * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers * with a net effect resembling a 2-level page table in normal x86 terms. Each @@ -1372,6 +1394,9 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) ppgtt->base.allocate_va_range = gen8_ppgtt_alloc_4lvl; ppgtt->base.insert_entries = gen8_ppgtt_insert_4lvl; ppgtt->base.clear_range = gen8_ppgtt_clear_4lvl; + + if (SUPPORTS_PAGE_SIZE(dev_priv, I915_GTT_PAGE_SIZE_64K)) + ppgtt->base.mm.color_adjust = i915_page_color_adjust; } else { ret = __pdp_init(&ppgtt->base, &ppgtt->pdp); if (ret) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 9c592e2de516..8d893ddd98f2 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -353,6 +353,12 @@ i915_vm_has_cache_coloring(const struct i915_address_space *vm) } static inline bool +i915_vm_has_page_coloring(const struct i915_address_space *vm) +{ + return vm->mm.color_adjust && !i915_is_ggtt(vm); +} + +static inline bool i915_vm_is_48bit(const struct i915_address_space *vm) { return (vm->total - 1) >> 32; diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 8f0041ba328f..4043145b4310 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -471,6 +471,8 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) if (i915_vm_has_cache_coloring(vma->vm)) color = obj->cache_level; + else if (i915_vm_has_page_coloring(vma->vm)) + color = obj->gtt_page_size; if (flags & PIN_OFFSET_FIXED) { u64 offset = flags & PIN_OFFSET_MASK;