From patchwork Wed Apr 12 15:55:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Robert Bragg X-Patchwork-Id: 9677693 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DFF5560383 for ; Wed, 12 Apr 2017 15:57:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D2A012818B for ; Wed, 12 Apr 2017 15:57:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C7A3028501; Wed, 12 Apr 2017 15:57:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 53FEB2818B for ; Wed, 12 Apr 2017 15:57:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DC5FD6E76C; Wed, 12 Apr 2017 15:57:11 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id 751686E76C for ; Wed, 12 Apr 2017 15:57:10 +0000 (UTC) Received: by mail-wm0-x244.google.com with SMTP id q125so7305976wmd.3 for ; Wed, 12 Apr 2017 08:57:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qEE/fjDfUZFj8YsUkuqenvgYyMOKRPS0I8ypQz2XJWs=; b=EQuHA9DfSWxQORy+gF95ctkQfaUCviWQyIx/QxQj8Glr8wj/UKnUhyQ2kOddSWuNVu qeTfx3SRblCqOph5wi0YEeB5NwTjEnPtC8L0PiIH47FIJ8KEkL3+WfeFBiSZg3vyaUEQ c3LTbyb1oLDUcyFhh3m2JdENkMaflFvwHwuuDC4ecTmd5unR5JCZ9CUqW3HWMOp4+qZH aKn+43GGi5SPBcdpQCC1E20XN45SJ8IAwEshalAHMiDejSWo2/4CnVEWhbE57DESb+E6 w+Lx+33W0UwHFJgIAwtgZeu0nfEh8cvIiv7tPLsYHGF7raCSY4Bi2GdS2cBxesN0ZqIx wWUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=qEE/fjDfUZFj8YsUkuqenvgYyMOKRPS0I8ypQz2XJWs=; b=YxxVE9OBRyaSBg7T/zuDU7o1+wyF0ZYO4mFC71So47D/Hmz8IUscCy+dkFgjRLuY6x Ofi2tTrK4MNWi8s6xRGQ4pyhj2Jdl3ovchE3DeJFcCbups8tQ103AOgxrv40WD7lBScX 9igL3Lja/TgkC7mO6zwPeeIHggjGzgPR70mQVKV9/OUvF+i+T+jy67lhh7ZmC4t5Dddw 9+1LDB66n8rOAugD7+VmURpTICiBGjoQV6XfUxIb5NXp7xdyrPL8fs4Cxt5FpFuYYnvF jHihTf1XmulUE6HEbFptQ9linPyb/hoAUj5wRhW8DHKV7epm38aspp7uNTJTjMCP5knv e34Q== X-Gm-Message-State: AN3rC/6Ot2lgY33way2Vw3W+BHXEhtoqbpJkFgwoIzNz2Op2YuFvigpl pacrKKEUd6doQEE8Y4Q= X-Received: by 10.28.63.22 with SMTP id m22mr21431512wma.142.1492012628891; Wed, 12 Apr 2017 08:57:08 -0700 (PDT) Received: from sixbynine.org (host-78-151-16-127.as13285.net. [78.151.16.127]) by smtp.gmail.com with ESMTPSA id d17sm7062338wmi.21.2017.04.12.08.57.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Apr 2017 08:57:08 -0700 (PDT) From: Robert Bragg To: intel-gfx@lists.freedesktop.org Date: Wed, 12 Apr 2017 16:55:55 +0100 Message-Id: <20170412155556.6602-15-robert@sixbynine.org> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170412155556.6602-1-robert@sixbynine.org> References: <20170412155556.6602-1-robert@sixbynine.org> MIME-Version: 1.0 Cc: Lionel Landwerlin Subject: [Intel-gfx] [PATCH v4 14/15] drm/i915/perf: per-gen timebase for checking sample freq X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP An oa_exponent_to_ns() utility and per-gen timebase constants where recently removed when updating the tail pointer race condition WA, and this restores those so we can update the _PROP_OA_EXPONENT validation done in read_properties_unlocked() to not assume we have a 12.5MHz timebase as we did for Haswell. Accordingly the oa_sample_rate_hard_limit value that's referenced by proc_dointvec_minmax defining the absolute limit for the OA sampling frequency is now initialized to (timestamp_frequency / 2) instead of the 6.25MHz constant for Haswell. v2: Specify frequency of 19.2MHz for BXT (Ville) Initialize oa_sample_rate_hard_limit per-gen too (Lionel) Signed-off-by: Robert Bragg Cc: Lionel Landwerlin Cc: Ville Syrjälä Reviewed-by: Matthew Auld Acked-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_perf.c | 37 ++++++++++++++++++++++++++----------- 2 files changed, 27 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b8dcf281db53..59dcce3b40a9 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2457,6 +2457,7 @@ struct drm_i915_private { bool periodic; int period_exponent; + int timestamp_frequency; int metrics_set; diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 611f996bece7..5de8d57e0b77 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -288,10 +288,12 @@ static u32 i915_perf_stream_paranoid = true; /* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate * - * 160ns is the smallest sampling period we can theoretically program the OA - * unit with on Haswell, corresponding to 6.25MHz. + * The highest sampling frequency we can theoretically program the OA unit + * with is always half the timestamp frequency: E.g. 6.25Mhz for Haswell. + * + * Initialized just before we register the sysctl parameter. */ -static int oa_sample_rate_hard_limit = 6250000; +static int oa_sample_rate_hard_limit; /* Theoretically we can program the OA unit to sample every 160ns but don't * allow that by default unless root... @@ -2560,6 +2562,12 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv, return ret; } +static u64 oa_exponent_to_ns(struct drm_i915_private *dev_priv, int exponent) +{ + return div_u64(1000000000ULL * (2ULL << exponent), + dev_priv->perf.oa.timestamp_frequency); +} + /** * read_properties_unlocked - validate + copy userspace stream open properties * @dev_priv: i915 device instance @@ -2656,16 +2664,13 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv, } /* Theoretically we can program the OA unit to sample - * every 160ns but don't allow that by default unless - * root. - * - * On Haswell the period is derived from the exponent - * as: - * - * period = 80ns * 2^(exponent + 1) + * e.g. every 160ns for HSW, 167ns for BDW/SKL or 104ns + * for BXT. We don't allow such high sampling + * frequencies by default unless root. */ + BUILD_BUG_ON(sizeof(oa_period) != 8); - oa_period = 80ull * (2ull << value); + oa_period = oa_exponent_to_ns(dev_priv, value); /* This check is primarily to ensure that oa_period <= * UINT32_MAX (before passing to do_div which only @@ -2921,6 +2926,8 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.ops.oa_hw_tail_read = gen7_oa_hw_tail_read; + dev_priv->perf.oa.timestamp_frequency = 12500000; + dev_priv->perf.oa.oa_formats = hsw_oa_formats; dev_priv->perf.oa.n_builtin_sets = @@ -2934,6 +2941,8 @@ void i915_perf_init(struct drm_i915_private *dev_priv) */ if (IS_GEN8(dev_priv)) { + dev_priv->perf.oa.timestamp_frequency = 12500000; + dev_priv->perf.oa.ctx_oactxctrl_offset = 0x120; dev_priv->perf.oa.ctx_flexeu0_offset = 0x2ce; dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<25); @@ -2950,6 +2959,8 @@ void i915_perf_init(struct drm_i915_private *dev_priv) i915_oa_select_metric_set_chv; } } else if (IS_GEN9(dev_priv)) { + dev_priv->perf.oa.timestamp_frequency = 12000000; + dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128; dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de; dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16); @@ -2970,6 +2981,8 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.ops.select_metric_set = i915_oa_select_metric_set_sklgt4; } else if (IS_BROXTON(dev_priv)) { + dev_priv->perf.oa.timestamp_frequency = 19200000; + dev_priv->perf.oa.n_builtin_sets = i915_oa_n_builtin_metric_sets_bxt; dev_priv->perf.oa.ops.select_metric_set = @@ -3004,6 +3017,8 @@ void i915_perf_init(struct drm_i915_private *dev_priv) spin_lock_init(&dev_priv->perf.hook_lock); spin_lock_init(&dev_priv->perf.oa.oa_buffer.ptr_lock); + oa_sample_rate_hard_limit = + dev_priv->perf.oa.timestamp_frequency / 2; dev_priv->perf.sysctl_header = register_sysctl_table(dev_root); dev_priv->perf.initialized = true;