From patchwork Tue Apr 18 20:23:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michel Thierry X-Patchwork-Id: 9686251 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4526A602C2 for ; Tue, 18 Apr 2017 20:23:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 35DE8283A6 for ; Tue, 18 Apr 2017 20:23:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2AC64283F1; Tue, 18 Apr 2017 20:23:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B6896283A6 for ; Tue, 18 Apr 2017 20:23:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A12796E255; Tue, 18 Apr 2017 20:23:39 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 456136E230 for ; Tue, 18 Apr 2017 20:23:38 +0000 (UTC) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP; 18 Apr 2017 13:23:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,219,1488873600"; d="scan'208,223";a="1157703323" Received: from relo-linux-11.sc.intel.com ([10.3.160.214]) by fmsmga002.fm.intel.com with ESMTP; 18 Apr 2017 13:23:36 -0700 From: Michel Thierry To: intel-gfx@lists.freedesktop.org Date: Tue, 18 Apr 2017 13:23:35 -0700 Message-Id: <20170418202335.35232-21-michel.thierry@intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170418202335.35232-1-michel.thierry@intel.com> References: <20170418202335.35232-1-michel.thierry@intel.com> Subject: [Intel-gfx] [PATCH v6 20/20] drm/i915: Watchdog timeout: Export media reset count from GuC to debugfs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From firmware v8.8, GuC provides the count of media engine resets (watchdog timeout). This information is available in the GuC shared context data struct, which resides in the first page of the default (kernel) lrc context. Since GuC handled engine resets are transparent for kernel and user, provide a simple debugfs entry to see the number of times media reset has happened. v2: Remove unnecessary struct_mutex, _get_dirty_page and kmap_atomic; use READ_ONCE. (Chris) Cc: Chris Wilson Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_debugfs.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/i915/intel_guc_fwif.h | 18 ++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 6444c1a9bd22..35ce771c8b8f 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1403,6 +1403,26 @@ static int i915_hangcheck_info(struct seq_file *m, void *unused) return 0; } +static u32 i915_watchdog_reset_count(struct drm_i915_private *dev_priv) +{ + struct i915_gem_context *ctx; + struct page *page; + struct guc_shared_ctx_data *guc_shared_data; + u32 guc_media_reset_count; + + if (!i915.enable_guc_submission) + return 0; + + ctx = dev_priv->kernel_context; + page = i915_gem_object_get_page(ctx->engine[RCS].state->obj, + LRC_GUCSHR_PN); + guc_shared_data = kmap(page); + guc_media_reset_count = READ_ONCE(guc_shared_data->media_reset_count); + kunmap(page); + + return guc_media_reset_count; +} + static int i915_reset_info(struct seq_file *m, void *unused) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -1411,6 +1431,8 @@ static int i915_reset_info(struct seq_file *m, void *unused) enum intel_engine_id id; seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error)); + seq_printf(m, "GuC watchdog/media reset = %u\n", + i915_watchdog_reset_count(dev_priv)); for_each_engine(engine, dev_priv, id) { seq_printf(m, "%s = %u\n", engine->name, diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index a2d0cba2f8b9..e45987f7aa50 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -502,6 +502,24 @@ union guc_log_control { u32 value; } __packed; +/* GuC Shared Context Data Struct */ +struct guc_shared_ctx_data { + u32 addr_of_last_preempted_data_low; + u32 addr_of_last_preempted_data_high; + u32 addr_of_last_preempted_data_high_tmp; + u32 padding; + u32 is_mapped_to_proxy; + u32 proxy_ctx_id; + u32 engine_reset_ctx_id; + u32 media_reset_count; + u32 reserved[8]; + u32 uk_last_ctx_switch_reason; + u32 was_reset; + u32 lrca_gpu_addr; + u32 execlist_ctx; + u32 reserved1[32]; +} __packed; + /* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */ enum intel_guc_action { INTEL_GUC_ACTION_DEFAULT = 0x0,