From patchwork Mon May 8 08:50:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 9715897 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id ED753602A0 for ; Mon, 8 May 2017 08:50:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E0D402097A for ; Mon, 8 May 2017 08:50:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D24362003F; Mon, 8 May 2017 08:50:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 85E152003F for ; Mon, 8 May 2017 08:50:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7BCA16E189; Mon, 8 May 2017 08:50:20 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 066996E189 for ; Mon, 8 May 2017 08:50:20 +0000 (UTC) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP; 08 May 2017 01:50:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,308,1491289200"; d="scan'208";a="84832093" Received: from linux.intel.com ([10.54.29.200]) by orsmga004.jf.intel.com with ESMTP; 08 May 2017 01:50:18 -0700 Received: from localhost (aconselv-mobl3.fi.intel.com [10.237.66.54]) by linux.intel.com (Postfix) with ESMTP id EB18D6A4006; Mon, 8 May 2017 01:50:04 -0700 (PDT) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org Date: Mon, 8 May 2017 11:50:03 +0300 Message-Id: <20170508085003.29086-1-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 2.9.3 Cc: Ander Conselvan de Oliveira Subject: [Intel-gfx] [PATCH] drm/i915: Work around for underrun when enabling pipe scaler in GLK X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP In Geminilake, a FIFO underrun happens the first time a pipe scaler is enabled after boot/resume from suspend. Disabling DPF clock gating in the respective CLKGATE_DIS_PSL register prior to enabling the scaler works around the issue. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ drivers/gpu/drm/i915/intel_display.c | 17 +++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 524fdfd..3157c39 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3424,6 +3424,14 @@ enum { #define PWM2_GATING_DIS (1 << 14) #define PWM1_GATING_DIS (1 << 13) +#define _CLKGATE_DIS_PSL_A 0x46520 +#define _CLKGATE_DIS_PSL_B 0x46524 +#define _CLKGATE_DIS_PSL_C 0x46528 +#define DPF_GATING_DIS (1 << 10) + +#define CLKGATE_DIS_PSL(pipe) \ + _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B) + /* * Display engine regs */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 85b9e2f5..c24acdd 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3176,6 +3176,7 @@ static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) static void skl_detach_scalers(struct intel_crtc *intel_crtc) { struct intel_crtc_scaler_state *scaler_state; + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); int i; scaler_state = &intel_crtc->config->scaler_state; @@ -3185,6 +3186,14 @@ static void skl_detach_scalers(struct intel_crtc *intel_crtc) if (!scaler_state->scalers[i].in_use) skl_detach_scaler(intel_crtc, i); } + + if (IS_GEMINILAKE(dev_priv)) { + u32 tmp; + + tmp = I915_READ(CLKGATE_DIS_PSL(intel_crtc->pipe)); + tmp &= ~DPF_GATING_DIS; + I915_WRITE(CLKGATE_DIS_PSL(intel_crtc->pipe), tmp); + } } u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, @@ -4763,6 +4772,14 @@ static void skylake_pfit_enable(struct intel_crtc *crtc) if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) return; + if (IS_GEMINILAKE(dev_priv)) { + u32 tmp; + + tmp = I915_READ(CLKGATE_DIS_PSL(crtc->pipe)); + tmp |= DPF_GATING_DIS; + I915_WRITE(CLKGATE_DIS_PSL(crtc->pipe), tmp); + } + id = scaler_state->scaler_id; I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);