From patchwork Tue May 16 08:29:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 9728553 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EB1206028A for ; Tue, 16 May 2017 08:30:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DAC5D289EC for ; Tue, 16 May 2017 08:30:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CC7F2289EA; Tue, 16 May 2017 08:30:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 78C8C289EA for ; Tue, 16 May 2017 08:30:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 92AF06E2E7; Tue, 16 May 2017 08:30:11 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id E87FA6E2DC for ; Tue, 16 May 2017 08:30:07 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP; 16 May 2017 01:30:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.38,348,1491289200"; d="scan'208"; a="1130912828" Received: from koreilly-mobl1.ger.corp.intel.com (HELO mwahaha.ger.corp.intel.com) ([10.252.21.88]) by orsmga001.jf.intel.com with ESMTP; 16 May 2017 01:30:06 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Date: Tue, 16 May 2017 09:29:41 +0100 Message-Id: <20170516082948.28090-11-matthew.auld@intel.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170516082948.28090-1-matthew.auld@intel.com> References: <20170516082948.28090-1-matthew.auld@intel.com> Subject: [Intel-gfx] [PATCH 10/17] drm/i915: support inserting 64K pages into the 48b PPGTT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP If we set the IPS bit, aka PDE[11] then every 16th entry should be used to index, the HW makes no assumptions for any other PTEs. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem_gtt.c | 74 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_gem_gtt.h | 2 + 2 files changed, 76 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 3be3cbfb6d28..874854e77247 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -854,6 +854,77 @@ static __always_inline struct gen8_insert_pte gen8_insert_pte(u64 start) } static __always_inline bool +gen8_ppgtt_insert_64K_pte_entries(struct i915_hw_ppgtt *ppgtt, + struct i915_page_directory_pointer *pdp, + struct sgt_dma *iter, + struct gen8_insert_pte *idx, + enum i915_cache_level cache_level) +{ + struct i915_page_directory *pd; + const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level); + gen8_pte_t *vaddr; + bool ret; + + /* Currently 64K objects should be aligned to 2M to prevent mixing 4K + * and 64K pte's in the same page-table. + */ + GEM_BUG_ON(idx->pte); + GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->base)); + pd = pdp->page_directory[idx->pdpe]; + + vaddr = kmap_atomic_px(pd); + vaddr[idx->pde] |= GEN8_PDE_IPS_64K; + kunmap_atomic(vaddr); + + vaddr = kmap_atomic_px(pd->page_table[idx->pde]); + do { + vaddr[idx->pte] = pte_encode | iter->dma; + iter->dma += I915_GTT_PAGE_SIZE_64K; + if (iter->dma >= iter->max) { + iter->sg = __sg_next(iter->sg); + if (!iter->sg) { + ret = false; + break; + } + + iter->dma = sg_dma_address(iter->sg); + iter->max = iter->dma + iter->sg->length; + } + + idx->pte += 16; + + if (idx->pte == GEN8_PTES) { + idx->pte = 0; + + if (++idx->pde == I915_PDES) { + idx->pde = 0; + + if (++idx->pdpe == GEN8_PML4ES_PER_PML4) { + idx->pdpe = 0; + ret = true; + break; + } + + GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->base)); + pd = pdp->page_directory[idx->pdpe]; + } + + kunmap_atomic(vaddr); + vaddr = kmap_atomic_px(pd); + vaddr[idx->pde] |= GEN8_PDE_IPS_64K; + kunmap_atomic(vaddr); + + vaddr = kmap_atomic_px(pd->page_table[idx->pde]); + } + } while (1); + kunmap_atomic(vaddr); + + mark_tlbs_dirty(ppgtt); + + return ret; +} + +static __always_inline bool gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt, struct i915_page_directory_pointer *pdp, struct sgt_dma *iter, @@ -954,6 +1025,9 @@ static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm, case I915_GTT_PAGE_SIZE_4K: insert_entries = gen8_ppgtt_insert_pte_entries; break; + case I915_GTT_PAGE_SIZE_64K: + insert_entries = gen8_ppgtt_insert_64K_pte_entries; + break; default: MISSING_CASE(page_size); return; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 5a2a3907d266..04d37c62c3ef 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -149,6 +149,8 @@ typedef u64 gen8_ppgtt_pml4e_t; #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) +#define GEN8_PDE_IPS_64K BIT(11) + struct sg_table; struct intel_rotation_info {