From patchwork Tue May 16 08:29:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 9728555 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C039D6028A for ; Tue, 16 May 2017 08:30:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B1680289EA for ; Tue, 16 May 2017 08:30:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A65D128A01; Tue, 16 May 2017 08:30:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6FE9B289EA for ; Tue, 16 May 2017 08:30:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B1C956E2E8; Tue, 16 May 2017 08:30:13 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2DBD86E2DC for ; Tue, 16 May 2017 08:30:09 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP; 16 May 2017 01:30:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.38,348,1491289200"; d="scan'208"; a="1130912847" Received: from koreilly-mobl1.ger.corp.intel.com (HELO mwahaha.ger.corp.intel.com) ([10.252.21.88]) by orsmga001.jf.intel.com with ESMTP; 16 May 2017 01:30:08 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Date: Tue, 16 May 2017 09:29:42 +0100 Message-Id: <20170516082948.28090-12-matthew.auld@intel.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170516082948.28090-1-matthew.auld@intel.com> References: <20170516082948.28090-1-matthew.auld@intel.com> Subject: [Intel-gfx] [PATCH 11/17] drm/i915: disable GTT cache for 2M/1G pages X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP When SW enables the use of 2M/1G pages, it must disable the GTT cache. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/intel_pm.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ef0e9f8d4dbd..b39b8d394179 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8178,10 +8178,10 @@ static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv) /* * WaGttCachingOffByDefault:bdw - * GTT cache may not work with big pages, so if those - * are ever enabled GTT cache may need to be disabled. + * The GTT cache must be disabled if the system is planning to use + * 2M/1G pages. */ - I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); + I915_WRITE(HSW_GTT_CACHE_EN, 0); /* WaKVMNotificationOnConfigChange:bdw */ I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1) @@ -8457,10 +8457,10 @@ static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv) gen8_set_l3sqc_credits(dev_priv, 38, 2); /* - * GTT cache may not work with big pages, so if those - * are ever enabled GTT cache may need to be disabled. + * The GTT cache must be disabled if the system is planning to use + * 2M/1G pages. */ - I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); + I915_WRITE(HSW_GTT_CACHE_EN, 0); } static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)