From patchwork Tue May 16 08:29:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 9728539 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C05656028A for ; Tue, 16 May 2017 08:29:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B0F51289EA for ; Tue, 16 May 2017 08:29:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A5D0D28A01; Tue, 16 May 2017 08:29:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2A92D289EA for ; Tue, 16 May 2017 08:29:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C00E06E2D4; Tue, 16 May 2017 08:29:56 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 67AC36E2D4 for ; Tue, 16 May 2017 08:29:55 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP; 16 May 2017 01:29:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.38,348,1491289200"; d="scan'208"; a="1130912712" Received: from koreilly-mobl1.ger.corp.intel.com (HELO mwahaha.ger.corp.intel.com) ([10.252.21.88]) by orsmga001.jf.intel.com with ESMTP; 16 May 2017 01:29:52 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Date: Tue, 16 May 2017 09:29:33 +0100 Message-Id: <20170516082948.28090-3-matthew.auld@intel.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170516082948.28090-1-matthew.auld@intel.com> References: <20170516082948.28090-1-matthew.auld@intel.com> Subject: [Intel-gfx] [PATCH 02/17] drm/i915: introduce gtt page size X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP In preparation for supporting huge gtt pages for the ppgtt, we introduce a gtt_page_size member for gem objects. We fill in the gtt page size by scanning the sg table to determine the max page size which satisfies the alignment for each sg entry. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gem.c | 23 +++++++++++++++++++++++ drivers/gpu/drm/i915/i915_gem_object.h | 2 ++ 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e18f11f77f35..a7a108d18a2d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2843,6 +2843,8 @@ intel_info(const struct drm_i915_private *dev_priv) #define USES_PPGTT(dev_priv) (i915.enable_ppgtt) #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2) #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3) +#define HAS_PAGE_SIZE(dev_priv, page_size) \ + ((dev_priv)->info.page_size_mask & (page_size)) #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay) #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 0c1cbe98c994..6a5e864d7710 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2294,6 +2294,8 @@ void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj, if (!IS_ERR(pages)) obj->ops->put_pages(obj, pages); + obj->gtt_page_size = 0; + unlock: mutex_unlock(&obj->mm.lock); } @@ -2473,6 +2475,13 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, struct sg_table *pages) { + struct drm_i915_private *i915 = to_i915(obj->base.dev); + unsigned long supported_page_sizes = INTEL_INFO(i915)->page_size_mask; + struct scatterlist *sg; + unsigned int sg_mask = 0; + unsigned int i; + unsigned int bit; + lockdep_assert_held(&obj->mm.lock); obj->mm.get_page.sg_pos = pages->sgl; @@ -2486,6 +2495,20 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, __i915_gem_object_pin_pages(obj); obj->mm.quirked = true; } + + for_each_sg(pages->sgl, sg, pages->nents, i) + sg_mask |= sg->length; + + GEM_BUG_ON(!sg_mask); + + for_each_set_bit(bit, &supported_page_sizes, BITS_PER_LONG) { + if (!IS_ALIGNED(sg_mask, 1 << bit)) + break; + + obj->gtt_page_size = 1 << bit; + } + + GEM_BUG_ON(!HAS_PAGE_SIZE(i915, obj->gtt_page_size)); } static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj) diff --git a/drivers/gpu/drm/i915/i915_gem_object.h b/drivers/gpu/drm/i915/i915_gem_object.h index 174cf923c236..75beb6a79635 100644 --- a/drivers/gpu/drm/i915/i915_gem_object.h +++ b/drivers/gpu/drm/i915/i915_gem_object.h @@ -107,6 +107,8 @@ struct drm_i915_gem_object { unsigned int cache_level:3; unsigned int cache_dirty:1; + unsigned int gtt_page_size; + atomic_t frontbuffer_bits; unsigned int frontbuffer_ggtt_origin; /* write once */ struct i915_gem_active frontbuffer_write;