From patchwork Wed May 17 00:34:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Puthikorn Voravootivat X-Patchwork-Id: 9729831 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1BBE760138 for ; Wed, 17 May 2017 00:34:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0E1BC201F3 for ; Wed, 17 May 2017 00:34:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 02EDD286C4; Wed, 17 May 2017 00:34:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9D03A201F3 for ; Wed, 17 May 2017 00:34:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B980C6E392; Wed, 17 May 2017 00:34:27 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pg0-x231.google.com (mail-pg0-x231.google.com [IPv6:2607:f8b0:400e:c05::231]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6CBF26E387 for ; Wed, 17 May 2017 00:34:22 +0000 (UTC) Received: by mail-pg0-x231.google.com with SMTP id u28so84045793pgn.1 for ; Tue, 16 May 2017 17:34:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=99yj1BlQHdFbwNNJ1OOmtPBKsXR2GzeipBVVbfO3Hx4=; b=UgrzJM9zbtbWhXfarXx8oqWNGsopnxAtZEgy8ZZH4ahHRUErWiwHYgxAT1KWBBHBu2 vXbNpnh8f7gvkmYUKyzdKpnW9oX6jlAOzn/JYT16f4/xCgwh676xlt3WHxPn0I1qJek1 2wngVg606gBj3BvXzOeApu/kIFQP5bCS2bZyIQUdj4yacH1MLUnwfKiW57gltsb/0wLk vJBc5e7QstU9vTWuRQZiygNyWdbFYYItFtc+0UnPtPS5t3DUfN1XJ+tcXRP15dvsZQLz Yfowzs4nO5X44k7Ycil+gVt5NRpuFH+JRcn2uevlJu5n+CISH9RNoobpDQfYAc8JyhGz LhsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=99yj1BlQHdFbwNNJ1OOmtPBKsXR2GzeipBVVbfO3Hx4=; b=RFJuSxCZY0BGp5eFsQ9AqewSLlPnCSsigpFT+0N//NZwpHoBwRlv8BIeqtPAO5DY97 OjCQMRLCNPrh6Tmpbg+f4F24OJvsEjigADzj4d4QglMksZNDIallBnCo7SoMVwG818Pr UjPBcFhQgDJ1qNco/dLPZ2gWDubI2ARn7tq5ae1YTIndZDSaQ64OSrqDptTzLPp+X3vk eYFQiNW0Sj3AQxhKekOj46631zDQJyXrzLiR4gyOiXfcUOrbwMjSw3ycCVdIjyBBmh80 O2J0jkxO1luTfugVt1jnbZAQqLWO0ipdh8WtdX5uZJF7iSxtDuDrHtzV5CTI908UVVKc /fbA== X-Gm-Message-State: AODbwcBkOFU0fda/K+s542cgXo+8f9X7MWBIIQqP6C8HZ8lErmx64zAu /ZxTVfcjcEirJXst X-Received: by 10.84.177.131 with SMTP id x3mr883086plb.39.1494981261805; Tue, 16 May 2017 17:34:21 -0700 (PDT) Received: from puthik2.mtv.corp.google.com ([172.22.64.53]) by smtp.gmail.com with ESMTPSA id b126sm365134pga.3.2017.05.16.17.34.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 May 2017 17:34:21 -0700 (PDT) Received: by puthik2.mtv.corp.google.com (Postfix, from userid 218808) id 2A65E11F8A3; Tue, 16 May 2017 17:34:20 -0700 (PDT) From: Puthikorn Voravootivat To: intel-gfx@lists.freedesktop.org, Dhinakaran Pandiyan Date: Tue, 16 May 2017 17:34:00 -0700 Message-Id: <20170517003403.152680-3-puthik@chromium.org> X-Mailer: git-send-email 2.13.0.303.g4ebf302169-goog In-Reply-To: <20170517003403.152680-1-puthik@chromium.org> References: <20170517003403.152680-1-puthik@chromium.org> Cc: Puthikorn Voravootivat , dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v8 2/5] drm/i915: Allow choosing how to adjust brightness if both supported X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Add option to allow choosing how to adjust brightness if panel supports both PWM pin and AUX channel. Signed-off-by: Puthikorn Voravootivat --- drivers/gpu/drm/i915/i915_params.c | 8 ++++--- drivers/gpu/drm/i915/i915_params.h | 2 +- drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 31 ++++++++++++++++++++++----- 3 files changed, 32 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index b6a7e363d076..13cf3f1572ab 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -63,7 +63,7 @@ struct i915_params i915 __read_mostly = { .huc_firmware_path = NULL, .enable_dp_mst = true, .inject_load_failure = 0, - .enable_dpcd_backlight = false, + .enable_dpcd_backlight = -1, .enable_gvt = false, }; @@ -246,9 +246,11 @@ MODULE_PARM_DESC(enable_dp_mst, module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 0400); MODULE_PARM_DESC(inject_load_failure, "Force an error after a number of failure check points (0:disabled (default), N:force failure at the Nth failure check point)"); -module_param_named(enable_dpcd_backlight, i915.enable_dpcd_backlight, bool, 0600); +module_param_named(enable_dpcd_backlight, i915.enable_dpcd_backlight, int, 0600); MODULE_PARM_DESC(enable_dpcd_backlight, - "Enable support for DPCD backlight control (default:false)"); + "Enable support for DPCD backlight control " + "(-1:disable (default), 0:Use PWM pin if both supported, " + "1:Use DPCD if both supported"); module_param_named(enable_gvt, i915.enable_gvt, bool, 0400); MODULE_PARM_DESC(enable_gvt, diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 34148cc8637c..ac02efce6e22 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -66,7 +66,7 @@ func(bool, verbose_state_checks); \ func(bool, nuclear_pageflip); \ func(bool, enable_dp_mst); \ - func(bool, enable_dpcd_backlight); \ + func(int, enable_dpcd_backlight); \ func(bool, enable_gvt) #define MEMBER(T, member) T member diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c index d32c06583e0b..16ba1924308d 100644 --- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c @@ -28,6 +28,10 @@ static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable) { uint8_t reg_val = 0; + /* Early return when display use other mechanism to enable backlight. */ + if (!(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)) + return; + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) < 0) { DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n", @@ -39,6 +43,9 @@ static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable) else reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE); + /* TODO: If the panel also support enabling backlight via BL_ENABLE pin, + * the backlight will be enabled again in _intel_edp_backlight_on() + */ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, reg_val) != 1) { DRM_DEBUG_KMS("Failed to %s aux backlight\n", @@ -164,21 +171,35 @@ intel_dp_aux_display_control_capable(struct intel_connector *connector) /* Check the eDP Display control capabilities registers to determine if * the panel can support backlight control over the aux channel */ - if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP && - (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) && - !((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_PIN_ENABLE_CAP) || - (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP))) { + if ((intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP) && + (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)) { DRM_DEBUG_KMS("AUX Backlight Control Supported!\n"); return true; } return false; } +static bool +intel_dp_pwm_pin_display_control_capable(struct intel_connector *connector) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base); + + /* Check the eDP Display control capabilities registers to determine if + * the panel can support backlight control via BL_PWM_DIM eDP pin + */ + return (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP) && + (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP); +} + int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector) { struct intel_panel *panel = &intel_connector->panel; - if (!i915.enable_dpcd_backlight) + if (i915.enable_dpcd_backlight == -1) + return -ENODEV; + + if (i915.enable_dpcd_backlight == 0 && + intel_dp_pwm_pin_display_control_capable(intel_connector)) return -ENODEV; if (!intel_dp_aux_display_control_capable(intel_connector))