From patchwork Fri May 19 13:23:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Micha=C5=82_Winiarski?= X-Patchwork-Id: 9737229 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 607776020B for ; Fri, 19 May 2017 13:25:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 58B54288B2 for ; Fri, 19 May 2017 13:25:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4CB26288F4; Fri, 19 May 2017 13:25:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CBC02288B2 for ; Fri, 19 May 2017 13:25:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 730DC6E699; Fri, 19 May 2017 13:25:04 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 373716E699 for ; Fri, 19 May 2017 13:25:03 +0000 (UTC) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP; 19 May 2017 06:25:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,364,1491289200"; d="scan'208";a="264005958" Received: from irsmsx102.ger.corp.intel.com ([163.33.3.155]) by fmsmga004.fm.intel.com with ESMTP; 19 May 2017 06:25:01 -0700 Received: from mwiniars-main.igk.intel.com (172.28.171.152) by IRSMSX102.ger.corp.intel.com (163.33.3.155) with Microsoft SMTP Server id 14.3.319.2; Fri, 19 May 2017 14:25:00 +0100 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= To: Date: Fri, 19 May 2017 15:23:20 +0200 Message-ID: <20170519132321.11953-5-michal.winiarski@intel.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170519132321.11953-1-michal.winiarski@intel.com> References: <20170519132321.11953-1-michal.winiarski@intel.com> MIME-Version: 1.0 X-Originating-IP: [172.28.171.152] Subject: [Intel-gfx] [PATCH v2 5/6] drm/i915/scheduler: Split insert_request X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP We'd like to reuse the priolist lookup in request resubmission path, let's split insert_request to make that happen. v2: Handle allocation error in lookup rather than in caller (Chris) Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Tvrtko Ursulin Signed-off-by: Michał Winiarski --- drivers/gpu/drm/i915/intel_lrc.c | 41 ++++++++++++++++++++++++---------------- 1 file changed, 25 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 1255724..8fc852c 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -627,20 +627,16 @@ static void intel_lrc_irq_handler(unsigned long data) intel_uncore_forcewake_put(dev_priv, engine->fw_domains); } -static bool -insert_request(struct intel_engine_cs *engine, - struct i915_priotree *pt, - int prio) +static struct i915_priolist * +priolist_lookup(struct intel_engine_cs *engine, int prio, bool *first) { struct i915_priolist *p; struct rb_node **parent, *rb; - bool first = true; +find_priolist: if (unlikely(engine->no_priolist)) prio = I915_PRIORITY_NORMAL; - -find_priolist: - /* most positive priority is scheduled first, equal priorities fifo */ + *first = true; rb = NULL; parent = &engine->execlist_queue.rb_node; while (*parent) { @@ -650,10 +646,10 @@ insert_request(struct intel_engine_cs *engine, parent = &rb->rb_left; } else if (prio < p->priority) { parent = &rb->rb_right; - first = false; + *first = false; } else { - list_add_tail(&pt->link, &p->requests); - return false; + *first = false; + return p; } } @@ -661,10 +657,8 @@ insert_request(struct intel_engine_cs *engine, p = &engine->default_priolist; } else { p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC); - /* Convert an allocation failure to a priority bump */ - if (unlikely(!p)) { - prio = I915_PRIORITY_NORMAL; /* recurses just once */ + if (unlikely(!p)) { /* To maintain ordering with all rendering, after an * allocation failure we have to disable all scheduling. * Requests will then be executed in fifo, and schedule @@ -683,11 +677,26 @@ insert_request(struct intel_engine_cs *engine, rb_insert_color(&p->node, &engine->execlist_queue); INIT_LIST_HEAD(&p->requests); - list_add_tail(&pt->link, &p->requests); - if (first) + if (*first) engine->execlist_first = &p->node; + return p; +} + +static bool +insert_request(struct intel_engine_cs *engine, + struct i915_priotree *pt, + int prio) +{ + struct i915_priolist *p; + bool first = false; + + p = priolist_lookup(engine, prio, &first); + + /* most positive priority is scheduled first, equal priorities fifo */ + list_add_tail(&pt->link, &p->requests); + return first; }