From patchwork Mon May 22 17:46:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michel Thierry X-Patchwork-Id: 9741223 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 540CA601C2 for ; Mon, 22 May 2017 17:46:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4499B28723 for ; Mon, 22 May 2017 17:46:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3985C2872A; Mon, 22 May 2017 17:46:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C8BC828723 for ; Mon, 22 May 2017 17:46:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C00FB6E25E; Mon, 22 May 2017 17:46:56 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2321F6E259 for ; Mon, 22 May 2017 17:46:47 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 May 2017 10:46:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,378,1491289200"; d="scan'208";a="860055350" Received: from relo-linux-11.sc.intel.com ([10.3.160.214]) by FMSMGA003.fm.intel.com with ESMTP; 22 May 2017 10:46:43 -0700 From: Michel Thierry To: intel-gfx@lists.freedesktop.org Date: Mon, 22 May 2017 10:46:32 -0700 Message-Id: <20170522174641.25354-12-michel.thierry@intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170522174641.25354-1-michel.thierry@intel.com> References: <20170522174641.25354-1-michel.thierry@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v8 11/20] drm/i915/guc: fix mmio whitelist mmio_start offset and add reminder X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Daniele Ceraolo Spurio The mmio_start offset for the whitelist is the first FORCE_TO_NONPRIV register the GuC can use to restore the provided whitelist when an engine reset via GuC (which we still don't support) is triggered. We're currently adding the mmio_base of the engine to the absolute address of the RCS version of the register, which results in the wrong offset. Fix it by using the definition we already have instead of re-defining it in the GuC FW header. Also add a comment to avoid future issues with FORCE_TO_NONPRIV registers, which are also used by the workaround framework. v2: improve comment (Michal), move comment about save/restore because it is not related to the mmio_white_list field. v3: rebase/resurrect. Signed-off-by: Daniele Ceraolo Spurio Cc: Michał Winiarski Cc: Michal Wajdeczko Cc: Arkadiusz Hiler Cc: Oscar Mateo Reviewed-by: Michał Winiarski (v2) Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_guc_submission.c | 11 +++++++++-- drivers/gpu/drm/i915/intel_guc_fwif.h | 1 - 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index 777f48e9bb33..50d3e5aaf566 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -1050,10 +1050,17 @@ static int guc_ads_create(struct intel_guc *guc) /* MMIO reg state */ for_each_engine(engine, dev_priv, id) { blob->reg_state.white_list[engine->guc_id].mmio_start = - engine->mmio_base + GUC_MMIO_WHITE_LIST_START; + i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(engine->mmio_base, 0)); - /* Nothing to be saved or restored for now. */ + /* + * Note: if the GuC whitelist management is enabled, the values + * should be filled using the workaround framework to avoid + * inconsistencies with the handling of FORCE_TO_NONPRIV + * registers. + */ blob->reg_state.white_list[engine->guc_id].count = 0; + + /* Nothing to be saved or restored for now. */ } /* diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index 6156845641a3..e6f8079df94a 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -394,7 +394,6 @@ struct guc_policies { #define GUC_REGSET_SAVE_CURRENT_VALUE 0x10 #define GUC_REGSET_MAX_REGISTERS 25 -#define GUC_MMIO_WHITE_LIST_START 0x24d0 #define GUC_MMIO_WHITE_LIST_MAX 12 #define GUC_S3_SAVE_SPACE_PAGES 10