From patchwork Mon May 22 17:46:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michel Thierry X-Patchwork-Id: 9741239 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4AB4D601C2 for ; Mon, 22 May 2017 17:47:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3ADC528723 for ; Mon, 22 May 2017 17:47:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2FA1C2872A; Mon, 22 May 2017 17:47:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7EB4028723 for ; Mon, 22 May 2017 17:47:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3D9606E271; Mon, 22 May 2017 17:47:03 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id A7B856E259 for ; Mon, 22 May 2017 17:46:49 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 May 2017 10:46:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,378,1491289200"; d="scan'208";a="860055334" Received: from relo-linux-11.sc.intel.com ([10.3.160.214]) by FMSMGA003.fm.intel.com with ESMTP; 22 May 2017 10:46:43 -0700 From: Michel Thierry To: intel-gfx@lists.freedesktop.org Date: Mon, 22 May 2017 10:46:38 -0700 Message-Id: <20170522174641.25354-18-michel.thierry@intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170522174641.25354-1-michel.thierry@intel.com> References: <20170522174641.25354-1-michel.thierry@intel.com> Subject: [Intel-gfx] [PATCH v8 17/20] drm/i915: Watchdog timeout: Ringbuffer command emission for gen8+ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Emit the required commands into the ring buffer for starting and stopping the watchdog timer before/after batch buffer start during batch buffer submission. v2: Support watchdog threshold per context engine, merge lri commands, and move watchdog commands emission to emit_bb_start. Request space of combined start_watchdog, bb_start and stop_watchdog to avoid any error after emitting bb_start. v3: There were too many req->engine in emit_bb_start. Use GEM_BUG_ON instead of returning a very late EINVAL in the remote case of watchdog misprogramming; set correct LRI cmd size in emit_stop_watchdog. (Chris) Cc: Chris Wilson Signed-off-by: Tomas Elf Signed-off-by: Ian Lister Signed-off-by: Arun Siluvery Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_context.h | 4 ++ drivers/gpu/drm/i915/intel_lrc.c | 85 +++++++++++++++++++++++++++++++-- drivers/gpu/drm/i915/intel_ringbuffer.h | 4 ++ 3 files changed, 89 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h index 4af2ab94558b..88700bdbb4e1 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.h +++ b/drivers/gpu/drm/i915/i915_gem_context.h @@ -150,6 +150,10 @@ struct i915_gem_context { u32 *lrc_reg_state; u64 lrc_desc; int pin_count; + /** watchdog_threshold: hw watchdog threshold value, + * in clock counts + */ + u32 watchdog_threshold; bool initialised; } engine[I915_NUM_ENGINES]; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 144bb9abd400..d7a6ba48cd18 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1386,7 +1386,10 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req, u64 offset, u32 len, const unsigned int flags) { + struct intel_engine_cs *engine = req->engine; u32 *cs; + u32 num_dwords; + bool watchdog_running = false; int ret; /* Don't rely in hw updating PDPs, specially in lite-restore. @@ -1396,20 +1399,38 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req, * not idle). PML4 is allocated during ppgtt init so this is * not needed in 48-bit.*/ if (req->ctx->ppgtt && - (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings) && + (intel_engine_flag(engine) & req->ctx->ppgtt->pd_dirty_rings) && !i915_vm_is_48bit(&req->ctx->ppgtt->base) && !intel_vgpu_active(req->i915)) { ret = intel_logical_ring_emit_pdps(req); if (ret) return ret; - req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine); + req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine); + } + + /* bb_start only */ + num_dwords = 4; + + /* check if watchdog will be required */ + if (req->ctx->engine[engine->id].watchdog_threshold != 0) { + GEM_BUG_ON(!engine->emit_start_watchdog || + !engine->emit_stop_watchdog); + + /* + start_watchdog (6) + stop_watchdog (4) */ + num_dwords += 10; + watchdog_running = true; } - cs = intel_ring_begin(req, 4); + cs = intel_ring_begin(req, num_dwords); if (IS_ERR(cs)) return PTR_ERR(cs); + if (watchdog_running) { + /* Start watchdog timer */ + cs = engine->emit_start_watchdog(req, cs); + } + /* FIXME(BDW): Address space and security selectors. */ *cs++ = MI_BATCH_BUFFER_START_GEN8 | (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) | @@ -1417,8 +1438,13 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req, *cs++ = lower_32_bits(offset); *cs++ = upper_32_bits(offset); *cs++ = MI_NOOP; - intel_ring_advance(req, cs); + if (watchdog_running) { + /* Cancel watchdog timer */ + cs = engine->emit_stop_watchdog(req, cs); + } + + intel_ring_advance(req, cs); return 0; } @@ -1585,6 +1611,49 @@ static void gen8_watchdog_irq_handler(unsigned long data) intel_uncore_forcewake_put(dev_priv, engine->fw_domains); } +static u32 *gen8_emit_start_watchdog(struct drm_i915_gem_request *req, u32 *cs) +{ + struct intel_engine_cs *engine = req->engine; + struct i915_gem_context *ctx = req->ctx; + struct intel_context *ce = &ctx->engine[engine->id]; + + /* XXX: no watchdog support in BCS engine */ + GEM_BUG_ON(engine->id == BCS); + + /* + * watchdog register must never be programmed to zero. This would + * cause the watchdog counter to exceed and not allow the engine to + * go into IDLE state + */ + GEM_BUG_ON(ce->watchdog_threshold == 0); + + /* Set counter period */ + *cs++ = MI_LOAD_REGISTER_IMM(2); + *cs++ = i915_mmio_reg_offset(RING_THRESH(engine->mmio_base)); + *cs++ = ce->watchdog_threshold; + /* Start counter */ + *cs++ = i915_mmio_reg_offset(RING_CNTR(engine->mmio_base)); + *cs++ = GEN8_WATCHDOG_ENABLE; + *cs++ = MI_NOOP; + + return cs; +} + +static u32 *gen8_emit_stop_watchdog(struct drm_i915_gem_request *req, u32 *cs) +{ + struct intel_engine_cs *engine = req->engine; + + /* XXX: no watchdog support in BCS engine */ + GEM_BUG_ON(engine->id == BCS); + + *cs++ = MI_LOAD_REGISTER_IMM(1); + *cs++ = i915_mmio_reg_offset(RING_CNTR(engine->mmio_base)); + *cs++ = get_watchdog_disable(engine); + *cs++ = MI_NOOP; + + return cs; +} + /* * Reserve space for 2 NOOPs at the end of each request to be * used as a workaround for not being allowed to do lite @@ -1853,6 +1922,8 @@ int logical_render_ring_init(struct intel_engine_cs *engine) engine->emit_flush = gen8_emit_flush_render; engine->emit_breadcrumb = gen8_emit_breadcrumb_render; engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz; + engine->emit_start_watchdog = gen8_emit_start_watchdog; + engine->emit_stop_watchdog = gen8_emit_stop_watchdog; ret = intel_engine_create_scratch(engine, PAGE_SIZE); if (ret) @@ -1876,6 +1947,12 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine) { logical_ring_setup(engine); + /* BCS engine does not have a watchdog-expired irq */ + if (engine->id != BCS) { + engine->emit_start_watchdog = gen8_emit_start_watchdog; + engine->emit_stop_watchdog = gen8_emit_stop_watchdog; + } + return logical_ring_init(engine); } diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 3906b33f5e74..13a2bae8462a 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -277,6 +277,10 @@ struct intel_engine_cs { int (*emit_flush)(struct drm_i915_gem_request *request, u32 mode); + u32 * (*emit_start_watchdog)(struct drm_i915_gem_request *req, + u32 *cs); + u32 * (*emit_stop_watchdog)(struct drm_i915_gem_request *req, + u32 *cs); #define EMIT_INVALIDATE BIT(0) #define EMIT_FLUSH BIT(1) #define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH)