From patchwork Fri May 26 15:15:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Mahesh" X-Patchwork-Id: 9750659 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 155E260249 for ; Fri, 26 May 2017 15:12:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 06799283DA for ; Fri, 26 May 2017 15:12:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EF66B28401; Fri, 26 May 2017 15:12:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AEDC2283DA for ; Fri, 26 May 2017 15:12:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 32EA96EDAE; Fri, 26 May 2017 15:12:14 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1DAD96EDAA for ; Fri, 26 May 2017 15:12:13 +0000 (UTC) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 May 2017 08:12:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,397,1491289200"; d="scan'208";a="107384300" Received: from kumarmah-desk.iind.intel.com ([10.223.26.44]) by fmsmga006.fm.intel.com with ESMTP; 26 May 2017 08:12:10 -0700 From: Mahesh Kumar To: intel-gfx@lists.freedesktop.org Date: Fri, 26 May 2017 20:45:44 +0530 Message-Id: <20170526151546.25025-2-mahesh1.kumar@intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170526151546.25025-1-mahesh1.kumar@intel.com> References: <20170526151546.25025-1-mahesh1.kumar@intel.com> Cc: paulo.r.zanoni@intel.com, maarten.lankhorst@intel.com Subject: [Intel-gfx] [PATCH 1/3] drm/i915/skl+: Don't trust cached ddb values X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Don't trust cached DDB values. Recalculate the ddb value if cached value is zero. If i915 is build as a module, there may be a race condition when cursor_disable call comes even before intel_fbdev_initial_config. Which may lead to cached value being 0. And further commit will fail until a modeset. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 936eef1634c7..b67be1355e39 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3721,6 +3721,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, struct drm_i915_private *dev_priv = to_i915(dev); struct drm_crtc *for_crtc = cstate->base.crtc; unsigned int pipe_size, ddb_size; + unsigned int active_crtcs; int nth_active_pipe; if (WARN_ON(!state) || !cstate->base.active) { @@ -3731,10 +3732,11 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, } if (intel_state->active_pipe_changes) - *num_active = hweight32(intel_state->active_crtcs); + active_crtcs = intel_state->active_crtcs; else - *num_active = hweight32(dev_priv->active_crtcs); + active_crtcs = dev_priv->active_crtcs; + *num_active = hweight32(active_crtcs); ddb_size = INTEL_INFO(dev_priv)->ddb_size; WARN_ON(ddb_size == 0); @@ -3754,12 +3756,15 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, * copy from old state to be sure */ *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb; - return; + if (!skl_ddb_entry_size(alloc)) + DRM_DEBUG_KMS("Cached pipe DDB is 0 recalculate\n"); + else + return; } - nth_active_pipe = hweight32(intel_state->active_crtcs & + nth_active_pipe = hweight32(active_crtcs & (drm_crtc_mask(for_crtc) - 1)); - pipe_size = ddb_size / hweight32(intel_state->active_crtcs); + pipe_size = ddb_size / hweight32(active_crtcs); alloc->start = nth_active_pipe * ddb_size / *num_active; alloc->end = alloc->start + pipe_size; }