From patchwork Sat May 27 01:42:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Puthikorn Voravootivat X-Patchwork-Id: 9751395 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A88C960246 for ; Sat, 27 May 2017 01:42:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9A49228425 for ; Sat, 27 May 2017 01:42:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8F33C28462; Sat, 27 May 2017 01:42:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 38A8B28425 for ; Sat, 27 May 2017 01:42:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0261F6E070; Sat, 27 May 2017 01:42:56 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pg0-x22a.google.com (mail-pg0-x22a.google.com [IPv6:2607:f8b0:400e:c05::22a]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1746E6E06A for ; Sat, 27 May 2017 01:42:16 +0000 (UTC) Received: by mail-pg0-x22a.google.com with SMTP id u28so919453pgn.1 for ; Fri, 26 May 2017 18:42:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=1bByh9mi6/DJ9KUFEwwNi37ctkQoo90tf4QCP8zBS8Q=; b=Hb3G0tafU3OdLx51Gv5+qGvuRI074mdetmkKSuRqmjIhar2D6NmCdBSumZnUDxsseZ 0RJEgrUwHY8BnlulcsiN9RPI+gXTxsBMKRVgV7H7WtF8q9fqldiH+joWk7D4oFzNwOnG DDo53uvV5RGtpCMPh8lf8+QJOH18oIWBJDh/qKbbtAqN4HuNCNGUo+utsfyTjsYH2Gw6 zna/dV2iUv42dpYkYGBPhNw/heS0bpHesUQwytjXaeV6eyDiTA3dBvYU5Mc1UBvLpVjA mtgQu5YwveLQ91kETHsg9s++1hx4NlTpo2f/ixy7NmgfKbD6TT34V3MDy0R4WE6EBUx+ nuyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=1bByh9mi6/DJ9KUFEwwNi37ctkQoo90tf4QCP8zBS8Q=; b=bbLNhXpps3/HHNsabmYQZCP16aDJuuEkKAFSqZzEGKKKSZ8yH6aodof1HojYna7zJz CBVP5JFJpLf8a9hDX8MXurdGzu+HOi5gnVAASEPGC99LuN+810nqUustX2dPX6SaJQc/ zFcoSb9jbQTpUnmmRZnnoNGN39Gcry+46KE6ff9ai9Gp96rdbMLYyfbzuVNK9KoCkY5S MR2BA01iq7kX/NPtDa+zCWbRMze7hR4sd9t8TUmEt6KZdx093LVeGmmVGwq5S8/+FsNc wQPBR5bjGjnJJWXd+KeaflwHjuBZzcplZxocdlLbp9DiMMScGZaEmpxEFu2wp1RzR1Tk MRfQ== X-Gm-Message-State: AODbwcBc1D5+JrdknPNXHi2lyTQxd6GUwZn1qH3aPltTtQzxlFc7sMQm JbgDW92RuWHamof1 X-Received: by 10.99.39.69 with SMTP id n66mr5986952pgn.87.1495849335570; Fri, 26 May 2017 18:42:15 -0700 (PDT) Received: from puthik2.mtv.corp.google.com ([172.22.64.53]) by smtp.gmail.com with ESMTPSA id p4sm5928634pgf.21.2017.05.26.18.42.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 May 2017 18:42:14 -0700 (PDT) Received: by puthik2.mtv.corp.google.com (Postfix, from userid 218808) id 9C3C911F8F2; Fri, 26 May 2017 18:42:12 -0700 (PDT) From: Puthikorn Voravootivat To: intel-gfx@lists.freedesktop.org, Dhinakaran Pandiyan , Jani Nikula , Daniel Vetter Date: Fri, 26 May 2017 18:42:09 -0700 Message-Id: <20170527014209.186331-4-puthik@chromium.org> X-Mailer: git-send-email 2.13.0.219.gdb65acc882-goog In-Reply-To: <20170527014209.186331-1-puthik@chromium.org> References: <20170527014209.186331-1-puthik@chromium.org> Cc: Puthikorn Voravootivat , dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH v10 3/3] drm/i915: Set PWM divider to match desired frequency in vbt X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Read desired PWM frequency from panel vbt and calculate the value for divider in DPCD address 0x724 and 0x728 to have as many bits as possible for PWM duty cyle for granularity of brightness adjustment while the frequency divisor is still within 25% of the desired value. Signed-off-by: Puthikorn Voravootivat --- drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 79 +++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c index f55af41ce3bd..a8d485a29f29 100644 --- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c @@ -116,6 +116,81 @@ intel_dp_aux_set_dynamic_backlight_percent(struct intel_dp *intel_dp, } } +/* + * Set PWM Frequency divider to match desired frequency in vbt. + * The PWM Frequency is calculated as 27Mhz / (F x P). + * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the + * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h) + * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the + * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h) + */ +static int intel_dp_aux_set_pwm_freq(struct intel_connector *connector) +{ + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base); + int freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1; + u8 pn, pn_min, pn_max; + + /* Find desired value of (F x P) + * Note that, if F x P is out of supported range, the maximum value or + * minimum value will applied automatically. So no need to check that. + */ + freq = dev_priv->vbt.backlight.pwm_freq_hz; + DRM_DEBUG_KMS("VBT defined backlight frequency %u Hz\n", freq); + if (!freq) { + DRM_DEBUG_KMS("Use panel default backlight frequency\n"); + return -1; + } + + fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq); + + /* Use highest possible value of Pn for more granularity of brightness + * adjustment while satifying the conditions below. + * - Pn is in the range of Pn_min and Pn_max + * - F is in the range of 1 and 255 + * - FxP is within 25% of desired value. + * Note: 25% is arbitrary value and may need some tweak. + */ + if (drm_dp_dpcd_readb(&intel_dp->aux, + DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min) != 1) { + DRM_DEBUG_KMS("Failed to read pwmgen bit count cap min\n"); + return -EIO; + } + if (drm_dp_dpcd_readb(&intel_dp->aux, + DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max) != 1) { + DRM_DEBUG_KMS("Failed to read pwmgen bit count cap max\n"); + return -EIO; + } + pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK; + pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK; + + fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4); + fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4); + if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) { + DRM_DEBUG_KMS("VBT defined backlight frequency out of range\n"); + return -ERANGE; + } + + for (pn = pn_max; pn >= pn_min; pn--) { + f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255); + fxp_actual = f << pn; + if (fxp_min <= fxp_actual && fxp_actual <= fxp_max) + break; + } + + if (drm_dp_dpcd_writeb(&intel_dp->aux, + DP_EDP_PWMGEN_BIT_COUNT, pn) < 0) { + DRM_DEBUG_KMS("Failed to write aux pwmgen bit count\n"); + return -EIO; + } + if (drm_dp_dpcd_writeb(&intel_dp->aux, + DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) { + DRM_DEBUG_KMS("Failed to write aux backlight freq\n"); + return -EIO; + } + return 0; +} + static void intel_dp_aux_enable_backlight(struct intel_connector *connector) { struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base); @@ -152,6 +227,10 @@ static void intel_dp_aux_enable_backlight(struct intel_connector *connector) DRM_DEBUG_KMS("Enable dynamic brightness.\n"); } + if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) + if (!intel_dp_aux_set_pwm_freq(connector)) + new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE; + if (new_dpcd_buf != dpcd_buf) { if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf) < 0) {