From patchwork Wed May 31 18:52:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 9757975 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 65953602BF for ; Wed, 31 May 2017 18:52:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 59A302834A for ; Wed, 31 May 2017 18:52:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4E8442849E; Wed, 31 May 2017 18:52:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 98BA72834A for ; Wed, 31 May 2017 18:52:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A6F6F6E2F3; Wed, 31 May 2017 18:52:37 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id C2FA36E2E3 for ; Wed, 31 May 2017 18:52:25 +0000 (UTC) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 May 2017 11:52:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.39,275,1493708400"; d="scan'208"; a="1155033219" Received: from sgallagh-mobl1.ger.corp.intel.com (HELO mwahaha.ger.corp.intel.com) ([10.252.0.34]) by fmsmga001.fm.intel.com with ESMTP; 31 May 2017 11:52:24 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Date: Wed, 31 May 2017 19:52:05 +0100 Message-Id: <20170531185210.29189-11-matthew.auld@intel.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170531185210.29189-1-matthew.auld@intel.com> References: <20170531185210.29189-1-matthew.auld@intel.com> Subject: [Intel-gfx] [PATCH 10/15] drm/i915: support huge gtt pages for the 48b PPGTT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Support inserting huge gtt pages into the 48b PPGTT, including mixed-mode where we allow a mixture of gtt page sizes. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Chris Wilson Cc: Daniel Vetter --- drivers/gpu/drm/i915/i915_gem_gtt.c | 79 ++++++++++++++++++++++++++++++++++--- drivers/gpu/drm/i915/i915_gem_gtt.h | 5 +++ 2 files changed, 79 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 935656802f09..924aec4adf6d 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -934,17 +934,86 @@ static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm, u32 unused) { struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); + struct gen8_insert_pte idx = gen8_insert_pte(start); + struct i915_page_directory_pointer **pdps = ppgtt->pml4.pdps; + struct i915_page_directory_pointer *pdp = pdps[idx.pml4e]; + struct i915_page_directory *pd = pdp->page_directory[idx.pdpe]; + struct i915_page_table *pt = pd->page_table[idx.pde]; + gen8_pte_t *pdp_vaddr = kmap_atomic_px(pdp); + gen8_pte_t *pd_vaddr = kmap_atomic_px(pd); + gen8_pte_t *pt_vaddr = kmap_atomic_px(pt); + const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level); struct sgt_dma iter = { .sg = pages->sgl, .dma = sg_dma_address(iter.sg), .max = iter.dma + iter.sg->length, }; - struct i915_page_directory_pointer **pdps = ppgtt->pml4.pdps; - struct gen8_insert_pte idx = gen8_insert_pte(start); - while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++], &iter, - &idx, cache_level)) - GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4); + do { + unsigned int page_size; + + pt_vaddr[idx.pte] = pte_encode | iter.dma; + page_size = I915_GTT_PAGE_SIZE; + + if (!idx.pte && page_sizes->sg > I915_GTT_PAGE_SIZE) { + dma_addr_t remaining = iter.max - iter.dma; + + if (unlikely(page_sizes->sg & I915_GTT_PAGE_SIZE_1G) && + remaining >= I915_GTT_PAGE_SIZE_1G && !idx.pde) { + pdp_vaddr[idx.pdpe] = pte_encode | GEN8_PDPE_PS_1G | iter.dma; + page_size = I915_GTT_PAGE_SIZE_1G; + } else if (page_sizes->sg & I915_GTT_PAGE_SIZE_2M && + remaining >= I915_GTT_PAGE_SIZE_2M) { + pd_vaddr[idx.pde] = pte_encode | GEN8_PDE_PS_2M | iter.dma; + page_size = I915_GTT_PAGE_SIZE_2M; + /* We don't support 64K in mixed mode for now */ + } else if (page_sizes->sg == I915_GTT_PAGE_SIZE_64K) { + pd_vaddr[idx.pde] |= GEN8_PDE_IPS_64K; + } + } + + start += page_size; + iter.dma += page_size; + if (iter.dma >= iter.max) { + iter.sg = __sg_next(iter.sg); + if (!iter.sg) + break; + + iter.dma = sg_dma_address(iter.sg); + iter.max = iter.dma + iter.sg->length; + } + + idx.pte = gen8_pte_index(start); + if (!idx.pte) { + idx.pde = gen8_pde_index(start); + + if (!idx.pde) { + idx.pdpe = gen8_pdpe_index(start); + + if (!idx.pdpe) { + GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4); + pdp = pdps[idx.pml4e++]; + + kunmap_atomic(pdp_vaddr); + pdp_vaddr = kmap_atomic_px(pdp); + } + + pd = pdp->page_directory[idx.pdpe]; + + kunmap_atomic(pd_vaddr); + pd_vaddr = kmap_atomic_px(pd); + } + + pt = pd->page_table[idx.pde]; + + kunmap_atomic(pt_vaddr); + pt_vaddr = kmap_atomic_px(pt); + } + } while (1); + + kunmap_atomic(pt_vaddr); + kunmap_atomic(pd_vaddr); + kunmap_atomic(pdp_vaddr); } static void gen8_free_page_tables(struct i915_address_space *vm, diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index d45729b9da0c..0811859b3a55 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -149,6 +149,11 @@ typedef u64 gen8_ppgtt_pml4e_t; #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) +#define GEN8_PDE_IPS_64K BIT(11) +#define GEN8_PDE_PS_2M BIT(7) + +#define GEN8_PDPE_PS_1G BIT(7) + struct sg_table; struct intel_rotation_info {