From patchwork Mon Jun 5 21:56:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Puthikorn Voravootivat X-Patchwork-Id: 9767595 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CE0DC60353 for ; Mon, 5 Jun 2017 21:56:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C21D427F10 for ; Mon, 5 Jun 2017 21:56:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B6C8F2842E; Mon, 5 Jun 2017 21:56:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3397527F10 for ; Mon, 5 Jun 2017 21:56:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5153A89FEA; Mon, 5 Jun 2017 21:56:14 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pg0-x22b.google.com (mail-pg0-x22b.google.com [IPv6:2607:f8b0:400e:c05::22b]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1F78C89FE3 for ; Mon, 5 Jun 2017 21:56:13 +0000 (UTC) Received: by mail-pg0-x22b.google.com with SMTP id a70so18902902pge.3 for ; Mon, 05 Jun 2017 14:56:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=YV6YKsQu6cVuEKrq0s2OfJ3MIHOBAkzbuJqRXe/YJv4=; b=AQXYclvM5IPzuMTcwG3n8/DZBr6/Y2BGfvO5jYoPn1+9JKyCq6VC6JFttGBskB08vV UJKacC29TTjXQhvEvANr3cGMr35nHvX6HEkgiB36MVy+CnEPzJ8ZQ238hFxWrwT6XLCx LFJPeoy+zYpBgy1ZhPDpIYlCMONI42MuV8f4IJbv7LXATjcC2guT+Jzt62uj/oPVbNxm CKPFg7CjhO0Xab2CjP3ewBDuqq2wHaGoumkLWXnsRSgv4rzxd3M8C0rYQe712gVcKZ0o PMgLsgsfgXE4iS0Y8NCm3Qu7ig3zqWFtPfzE6eeeuxmk2Huo2Pxlkuj6vcFV41dHQEX4 IC/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=YV6YKsQu6cVuEKrq0s2OfJ3MIHOBAkzbuJqRXe/YJv4=; b=hqBILM+W4TNlFTz985tP7Vk72bOMaAixOt/vLyRhTJLKyAIC7MH8t4yWESohQNwFBS WKgBedo55uV7aRKK8Hvw8YQ/ubbJruBXhBWnaulXSloR6ekhW4okc7HBSmKLUJVC2QSt IbzOIpKjnyPCdb8RkIDnBPrXP8LwgzHo1qQMGcsDAF5uaXc0I55eKnIb2CnjXk6wNacO Spts++5FMRSbODTYO+2awWpfoGiSMXfLldEJSBo3NV6FNieOnxLMvKo3vMjF0qJu//M6 1J57SjOZ153YcJCQHI6+RaU9A5mR/rllDh+jZIo8ex3i5zRaZa+YOtnxpu6W2sS/GVWg nrtQ== X-Gm-Message-State: AODbwcCWL1pSQBzZBuq8x+Qx3xLd7UWIh9e5t+xw81lfHluo+0JeoRxy WD4id0R7SF1NWwze X-Received: by 10.98.18.148 with SMTP id 20mr3492722pfs.142.1496699772503; Mon, 05 Jun 2017 14:56:12 -0700 (PDT) Received: from puthik2.mtv.corp.google.com ([172.22.64.53]) by smtp.gmail.com with ESMTPSA id a187sm31650210pge.45.2017.06.05.14.56.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Jun 2017 14:56:11 -0700 (PDT) Received: by puthik2.mtv.corp.google.com (Postfix, from userid 218808) id BC59B11F87D; Mon, 5 Jun 2017 14:56:10 -0700 (PDT) From: Puthikorn Voravootivat To: intel-gfx@lists.freedesktop.org, Dhinakaran Pandiyan , Jani Nikula , Daniel Vetter Date: Mon, 5 Jun 2017 14:56:05 -0700 Message-Id: <20170605215607.27766-2-puthik@chromium.org> X-Mailer: git-send-email 2.13.0.506.g27d5fe0cd-goog In-Reply-To: <20170605215607.27766-1-puthik@chromium.org> References: <20170605215607.27766-1-puthik@chromium.org> Cc: Puthikorn Voravootivat , dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH RESEND v11 1/3] drm/i915: Set PWM divider to match desired frequency in vbt X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Read desired PWM frequency from panel vbt and calculate the value for divider in DPCD address 0x724 and 0x728 to have as many bits as possible for PWM duty cyle for granularity of brightness adjustment while the frequency divisor is still within 25% of the desired value. Signed-off-by: Puthikorn Voravootivat Reviewed-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 98 ++++++++++++++++++++++++--- 1 file changed, 90 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c index a0995c00fc84..6c64e1f75c4e 100644 --- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c @@ -97,11 +97,85 @@ intel_dp_aux_set_backlight(struct intel_connector *connector, u32 level) } } +/* + * Set PWM Frequency divider to match desired frequency in vbt. + * The PWM Frequency is calculated as 27Mhz / (F x P). + * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the + * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h) + * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the + * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h) + */ +static bool intel_dp_aux_set_pwm_freq(struct intel_connector *connector) +{ + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base); + int freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1; + u8 pn, pn_min, pn_max; + + /* Find desired value of (F x P) + * Note that, if F x P is out of supported range, the maximum value or + * minimum value will applied automatically. So no need to check that. + */ + freq = dev_priv->vbt.backlight.pwm_freq_hz; + DRM_DEBUG_KMS("VBT defined backlight frequency %u Hz\n", freq); + if (!freq) { + DRM_DEBUG_KMS("Use panel default backlight frequency\n"); + return false; + } + + fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq); + + /* Use highest possible value of Pn for more granularity of brightness + * adjustment while satifying the conditions below. + * - Pn is in the range of Pn_min and Pn_max + * - F is in the range of 1 and 255 + * - FxP is within 25% of desired value. + * Note: 25% is arbitrary value and may need some tweak. + */ + if (drm_dp_dpcd_readb(&intel_dp->aux, + DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min) != 1) { + DRM_DEBUG_KMS("Failed to read pwmgen bit count cap min\n"); + return false; + } + if (drm_dp_dpcd_readb(&intel_dp->aux, + DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max) != 1) { + DRM_DEBUG_KMS("Failed to read pwmgen bit count cap max\n"); + return false; + } + pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK; + pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK; + + fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4); + fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4); + if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) { + DRM_DEBUG_KMS("VBT defined backlight frequency out of range\n"); + return false; + } + + for (pn = pn_max; pn >= pn_min; pn--) { + f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255); + fxp_actual = f << pn; + if (fxp_min <= fxp_actual && fxp_actual <= fxp_max) + break; + } + + if (drm_dp_dpcd_writeb(&intel_dp->aux, + DP_EDP_PWMGEN_BIT_COUNT, pn) < 0) { + DRM_DEBUG_KMS("Failed to write aux pwmgen bit count\n"); + return false; + } + if (drm_dp_dpcd_writeb(&intel_dp->aux, + DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) { + DRM_DEBUG_KMS("Failed to write aux backlight freq\n"); + return false; + } + return true; +} + static void intel_dp_aux_enable_backlight(struct intel_connector *connector) { struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base); - uint8_t dpcd_buf = 0; - uint8_t edp_backlight_mode = 0; + uint8_t dpcd_buf, new_dpcd_buf, edp_backlight_mode; if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf) != 1) { @@ -110,18 +184,15 @@ static void intel_dp_aux_enable_backlight(struct intel_connector *connector) return; } + new_dpcd_buf = dpcd_buf; edp_backlight_mode = dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK; switch (edp_backlight_mode) { case DP_EDP_BACKLIGHT_CONTROL_MODE_PWM: case DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET: case DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT: - dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK; - dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD; - if (drm_dp_dpcd_writeb(&intel_dp->aux, - DP_EDP_BACKLIGHT_MODE_SET_REGISTER, dpcd_buf) < 0) { - DRM_DEBUG_KMS("Failed to write aux backlight mode\n"); - } + new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK; + new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD; break; /* Do nothing when it is already DPCD mode */ @@ -130,6 +201,17 @@ static void intel_dp_aux_enable_backlight(struct intel_connector *connector) break; } + if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) + if (intel_dp_aux_set_pwm_freq(connector)) + new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE; + + if (new_dpcd_buf != dpcd_buf) { + if (drm_dp_dpcd_writeb(&intel_dp->aux, + DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf) < 0) { + DRM_DEBUG_KMS("Failed to write aux backlight mode\n"); + } + } + set_aux_backlight_enable(intel_dp, true); intel_dp_aux_set_backlight(connector, connector->panel.backlight.level); }