From patchwork Tue Jun 13 13:12:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Mahesh" X-Patchwork-Id: 9783811 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A357D602DC for ; Tue, 13 Jun 2017 13:08:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9667B28557 for ; Tue, 13 Jun 2017 13:08:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8B5522858F; Tue, 13 Jun 2017 13:08:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3A10D28557 for ; Tue, 13 Jun 2017 13:08:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 78DB76E2F1; Tue, 13 Jun 2017 13:08:34 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 284586E2F1 for ; Tue, 13 Jun 2017 13:08:34 +0000 (UTC) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP; 13 Jun 2017 06:08:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.39,338,1493708400"; d="scan'208"; a="1159906022" Received: from unknown (HELO localhost.localdomain) ([10.223.25.241]) by fmsmga001.fm.intel.com with ESMTP; 13 Jun 2017 06:08:31 -0700 From: Mahesh Kumar To: intel-gfx@lists.freedesktop.org Date: Tue, 13 Jun 2017 18:42:02 +0530 Message-Id: <20170613131202.4492-10-mahesh1.kumar@intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170613131202.4492-1-mahesh1.kumar@intel.com> References: <20170613131202.4492-1-mahesh1.kumar@intel.com> Cc: paulo.r.zanoni@intel.com, maarten.lankhorst@intel.com Subject: [Intel-gfx] [PATCH 9/9] drm/i915/gen10: Calculate and enable transition WM X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP GEN > 9 require transition WM to be programmed if IPC is enabled. This patch calculates & enable transition WM for supported platforms. If transition WM is enabled, Plane read requests are sent at high priority until filling above the transition watermark, then the requests are sent at lower priority until dropping below the level-0 WM. The lower priority requests allow other memory clients to have better memory access. transition minimum is the minimum amount needed for trans_wm to work to ensure the demote does not happen before enough data has been read to meet the level 0 watermark requirements. transition amount is configurable value. Higher values will tend to cause longer periods of high priority reads followed by longer periods of lower priority reads. Tuning to lower values will tend to cause shorter periods of high and lower priority reads. Keeping transition amount to 0 in this patch. Signed-off-by: Mahesh Kumar Acked-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_pm.c | 51 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 48 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 55f9e1ae0a94..4bbe242643cf 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4197,6 +4197,15 @@ skl_enable_plane_wm_levels(const struct drm_i915_private *dev_priv, level_wm->plane_en = true; } } + + /* + * Unsupported GEN will have plane_res_b = 0 & transition WM for + * them will get disabled here. + */ + if (wm->trans_wm.plane_res_b && wm->trans_wm.plane_res_b < plane_ddb) + wm->trans_wm.plane_en = true; + else + wm->trans_wm.plane_en = false; } static int @@ -4640,13 +4649,48 @@ skl_compute_linetime_wm(struct intel_crtc_state *cstate) } static void skl_compute_transition_wm(struct intel_crtc_state *cstate, + struct skl_wm_params *wp, + struct skl_wm_level *wm_l0, struct skl_wm_level *trans_wm /* out */) { + struct drm_device *dev = cstate->base.crtc->dev; + const struct drm_i915_private *dev_priv = to_i915(dev); + uint16_t trans_min, trans_y_tile_min; + uint16_t trans_amount = 0; /* This is configurable amount */ + uint16_t trans_offset_b, res_blocks; + if (!cstate->base.active) return; - /* Until we know more, just disable transition WMs */ - trans_wm->plane_en = false; + /* Transition WM are not recommended by HW team for GEN9 */ + if (INTEL_GEN(dev_priv) <= 9) + return; + + /* Transition WM don't have any impact if ipc is disabled */ + if (!dev_priv->ipc_enabled) + return; + + if (INTEL_GEN(dev_priv) >= 10) + trans_min = 4; + + trans_offset_b = trans_min + trans_amount; + trans_y_tile_min = (uint16_t) mul_round_up_u32_fixed16(2, + wp->y_tile_minimum); + + if (wp->y_tiled) { + res_blocks = max(wm_l0->plane_res_b, trans_y_tile_min) + + trans_offset_b; + } else { + res_blocks = wm_l0->plane_res_b + trans_offset_b; + } + + res_blocks += 1; + + /* WA BUG:1938466 add one block for non y-tile planes */ + if (!wp->y_tiled && IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) + res_blocks += 1; + + trans_wm->plane_res_b = res_blocks; } static int skl_build_pipe_wm(struct intel_crtc_state *cstate, @@ -4685,7 +4729,8 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate, &wm_params, wm); if (ret) return ret; - skl_compute_transition_wm(cstate, &wm->trans_wm); + skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0], + &wm->trans_wm); } pipe_wm->linetime = skl_compute_linetime_wm(cstate);