From patchwork Tue Jun 13 13:11:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Mahesh" X-Patchwork-Id: 9783791 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 425F1602DC for ; Tue, 13 Jun 2017 13:08:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 33AE22856B for ; Tue, 13 Jun 2017 13:08:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 284B928591; Tue, 13 Jun 2017 13:08:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 23C902856B for ; Tue, 13 Jun 2017 13:08:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 109BA6E2D8; Tue, 13 Jun 2017 13:08:16 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2E94E6E2D8 for ; Tue, 13 Jun 2017 13:08:15 +0000 (UTC) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP; 13 Jun 2017 06:08:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.39,338,1493708400"; d="scan'208"; a="1159905906" Received: from unknown (HELO localhost.localdomain) ([10.223.25.241]) by fmsmga001.fm.intel.com with ESMTP; 13 Jun 2017 06:08:11 -0700 From: Mahesh Kumar To: intel-gfx@lists.freedesktop.org Date: Tue, 13 Jun 2017 18:41:54 +0530 Message-Id: <20170613131202.4492-2-mahesh1.kumar@intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170613131202.4492-1-mahesh1.kumar@intel.com> References: <20170613131202.4492-1-mahesh1.kumar@intel.com> Cc: paulo.r.zanoni@intel.com, maarten.lankhorst@intel.com Subject: [Intel-gfx] [PATCH 1/9] drm/i915: take-out common clamping code of fixed16 wrappers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This patch creates a new function for clamping u64 to fixed16. And make use of this function in other fixed16 wrappers. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/i915_drv.h | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 602fb3324484..33b162dbee4e 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -160,6 +160,14 @@ static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1, return max; } +static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val) +{ + uint_fixed_16_16_t fp; + WARN_ON(val >> 32); + fp.val = clamp_t(uint32_t, val, 0, ~0); + return fp; +} + static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val, uint_fixed_16_16_t d) { @@ -170,26 +178,21 @@ static inline uint32_t mul_round_up_u32_fixed16(uint32_t val, uint_fixed_16_16_t mul) { uint64_t intermediate_val; - uint32_t result; intermediate_val = (uint64_t) val * mul.val; intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16); WARN_ON(intermediate_val >> 32); - result = clamp_t(uint32_t, intermediate_val, 0, ~0); - return result; + return clamp_t(uint32_t, intermediate_val, 0, ~0); } static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val, uint_fixed_16_16_t mul) { uint64_t intermediate_val; - uint_fixed_16_16_t fp; intermediate_val = (uint64_t) val.val * mul.val; intermediate_val = intermediate_val >> 16; - WARN_ON(intermediate_val >> 32); - fp.val = clamp_t(uint32_t, intermediate_val, 0, ~0); - return fp; + return clamp_u64_to_fixed16(intermediate_val); } static inline uint_fixed_16_16_t fixed_16_16_div(uint32_t val, uint32_t d) @@ -203,15 +206,11 @@ static inline uint_fixed_16_16_t fixed_16_16_div(uint32_t val, uint32_t d) static inline uint_fixed_16_16_t fixed_16_16_div_u64(uint32_t val, uint32_t d) { - uint_fixed_16_16_t res; uint64_t interm_val; interm_val = (uint64_t)val << 16; interm_val = DIV_ROUND_UP_ULL(interm_val, d); - WARN_ON(interm_val >> 32); - res.val = (uint32_t) interm_val; - - return res; + return clamp_u64_to_fixed16(interm_val); } static inline uint32_t div_round_up_u32_fixed16(uint32_t val, @@ -229,12 +228,9 @@ static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val, uint_fixed_16_16_t mul) { uint64_t intermediate_val; - uint_fixed_16_16_t fp; intermediate_val = (uint64_t) val * mul.val; - WARN_ON(intermediate_val >> 32); - fp.val = (uint32_t) intermediate_val; - return fp; + return clamp_u64_to_fixed16(intermediate_val); } static inline const char *yesno(bool v)