From patchwork Tue Jun 13 19:33:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zanoni, Paulo R" X-Patchwork-Id: 9784511 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2B0A660212 for ; Tue, 13 Jun 2017 19:34:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1EFC22871B for ; Tue, 13 Jun 2017 19:34:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1340B28723; Tue, 13 Jun 2017 19:34:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 952742871B for ; Tue, 13 Jun 2017 19:34:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6CDB16E395; Tue, 13 Jun 2017 19:34:10 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 819C56E395 for ; Tue, 13 Jun 2017 19:34:07 +0000 (UTC) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Jun 2017 12:34:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,339,1493708400"; d="scan'208";a="113970129" Received: from przanoni-mobl.amr.corp.intel.com ([10.254.177.94]) by fmsmga005.fm.intel.com with ESMTP; 13 Jun 2017 12:34:06 -0700 From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Tue, 13 Jun 2017 16:33:47 -0300 Message-Id: <20170613193350.10528-5-paulo.r.zanoni@intel.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170613193350.10528-1-paulo.r.zanoni@intel.com> References: <20170613193350.10528-1-paulo.r.zanoni@intel.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 4/7] drm/i915: rename _PICK to _PICK3 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP All of the macros that call _PICK are named _X_3, so let's rename _PICK to _PICK3. The reason we're doing this is because we're going to have _PICK and _PICK2. Consider _PICK3 as the third variation of the PICK macros (well, actually it *is* the third variation...). Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 33 ++++++++++++++++----------------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1d5a0f8..d271098 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -48,11 +48,11 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); } -#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) +#define _PICK3(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) -#define _MMIO_PIPE3(pipe, ...) _MMIO(_PICK(pipe, __VA_ARGS__)) +#define _MMIO_PIPE3(pipe, ...) _MMIO(_PICK3(pipe, __VA_ARGS__)) #define _PLANE(plane, a, b) _PIPE(plane, a, b) #define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b) @@ -62,15 +62,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) -#define _MMIO_PORT3(port, ...) _MMIO(_PICK(port, __VA_ARGS__)) -#define _MMIO_PORT6(port, ...) _MMIO(_PICK(port, __VA_ARGS__)) -#define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f) \ - _MMIO(_PICK(port, a0, b, c, d, e, f) + (ln * (a1 - a0))) +#define _MMIO_PORT3(port, ...) _MMIO(_PICK3(port, __VA_ARGS__)) +#define _MMIO_PORT3_LN(port, ln, a0, a1, b, c, d, e, f) \ + _MMIO(_PICK3(port, a0, b, c, d, e, f) + (ln * (a1 - a0))) #define _PLL(pll, a, b) ((a) + (pll)*((b)-(a))) #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) -#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) +#define _PHY3(phy, ...) _PICK3(phy, __VA_ARGS__) #define _MMIO_PHY3(phy, ...) _MMIO(_PHY3(phy, __VA_ARGS__)) #define _MASKED_FIELD(mask, value) ({ \ @@ -1709,14 +1708,14 @@ enum skl_disp_power_wells { #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04 #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04 #define _CNL_PORT_PCS_DW1_LN0_F 0x162804 -#define CNL_PORT_PCS_DW1_GRP(port) _MMIO_PORT6(port, \ +#define CNL_PORT_PCS_DW1_GRP(port) _MMIO_PORT3(port, \ _CNL_PORT_PCS_DW1_GRP_AE, \ _CNL_PORT_PCS_DW1_GRP_B, \ _CNL_PORT_PCS_DW1_GRP_C, \ _CNL_PORT_PCS_DW1_GRP_D, \ _CNL_PORT_PCS_DW1_GRP_AE, \ _CNL_PORT_PCS_DW1_GRP_F) -#define CNL_PORT_PCS_DW1_LN0(port) _MMIO_PORT6(port, \ +#define CNL_PORT_PCS_DW1_LN0(port) _MMIO_PORT3(port, \ _CNL_PORT_PCS_DW1_LN0_AE, \ _CNL_PORT_PCS_DW1_LN0_B, \ _CNL_PORT_PCS_DW1_LN0_C, \ @@ -1735,14 +1734,14 @@ enum skl_disp_power_wells { #define _CNL_PORT_TX_DW2_LN0_C 0x162C48 #define _CNL_PORT_TX_DW2_LN0_D 0x162E48 #define _CNL_PORT_TX_DW2_LN0_F 0x162A48 -#define CNL_PORT_TX_DW2_GRP(port) _MMIO_PORT6(port, \ +#define CNL_PORT_TX_DW2_GRP(port) _MMIO_PORT3(port, \ _CNL_PORT_TX_DW2_GRP_AE, \ _CNL_PORT_TX_DW2_GRP_B, \ _CNL_PORT_TX_DW2_GRP_C, \ _CNL_PORT_TX_DW2_GRP_D, \ _CNL_PORT_TX_DW2_GRP_AE, \ _CNL_PORT_TX_DW2_GRP_F) -#define CNL_PORT_TX_DW2_LN0(port) _MMIO_PORT6(port, \ +#define CNL_PORT_TX_DW2_LN0(port) _MMIO_PORT3(port, \ _CNL_PORT_TX_DW2_LN0_AE, \ _CNL_PORT_TX_DW2_LN0_B, \ _CNL_PORT_TX_DW2_LN0_C, \ @@ -1764,14 +1763,14 @@ enum skl_disp_power_wells { #define _CNL_PORT_TX_DW4_LN0_C 0x162C50 #define _CNL_PORT_TX_DW4_LN0_D 0x162E50 #define _CNL_PORT_TX_DW4_LN0_F 0x162850 -#define CNL_PORT_TX_DW4_GRP(port) _MMIO_PORT6(port, \ +#define CNL_PORT_TX_DW4_GRP(port) _MMIO_PORT3(port, \ _CNL_PORT_TX_DW4_GRP_AE, \ _CNL_PORT_TX_DW4_GRP_B, \ _CNL_PORT_TX_DW4_GRP_C, \ _CNL_PORT_TX_DW4_GRP_D, \ _CNL_PORT_TX_DW4_GRP_AE, \ _CNL_PORT_TX_DW4_GRP_F) -#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO_PORT6_LN(port, ln, \ +#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO_PORT3_LN(port, ln, \ _CNL_PORT_TX_DW4_LN0_AE, \ _CNL_PORT_TX_DW4_LN1_AE, \ _CNL_PORT_TX_DW4_LN0_B, \ @@ -1794,14 +1793,14 @@ enum skl_disp_power_wells { #define _CNL_PORT_TX_DW5_LN0_C 0x162C54 #define _CNL_PORT_TX_DW5_LN0_D 0x162ED4 #define _CNL_PORT_TX_DW5_LN0_F 0x162854 -#define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \ +#define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT3(port, \ _CNL_PORT_TX_DW5_GRP_AE, \ _CNL_PORT_TX_DW5_GRP_B, \ _CNL_PORT_TX_DW5_GRP_C, \ _CNL_PORT_TX_DW5_GRP_D, \ _CNL_PORT_TX_DW5_GRP_AE, \ _CNL_PORT_TX_DW5_GRP_F) -#define CNL_PORT_TX_DW5_LN0(port) _MMIO_PORT6(port, \ +#define CNL_PORT_TX_DW5_LN0(port) _MMIO_PORT3(port, \ _CNL_PORT_TX_DW5_LN0_AE, \ _CNL_PORT_TX_DW5_LN0_B, \ _CNL_PORT_TX_DW5_LN0_C, \ @@ -1823,14 +1822,14 @@ enum skl_disp_power_wells { #define _CNL_PORT_TX_DW7_LN0_C 0x162C5C #define _CNL_PORT_TX_DW7_LN0_D 0x162EDC #define _CNL_PORT_TX_DW7_LN0_F 0x16285C -#define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \ +#define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT3(port, \ _CNL_PORT_TX_DW7_GRP_AE, \ _CNL_PORT_TX_DW7_GRP_B, \ _CNL_PORT_TX_DW7_GRP_C, \ _CNL_PORT_TX_DW7_GRP_D, \ _CNL_PORT_TX_DW7_GRP_AE, \ _CNL_PORT_TX_DW7_GRP_F) -#define CNL_PORT_TX_DW7_LN0(port) _MMIO_PORT6(port, \ +#define CNL_PORT_TX_DW7_LN0(port) _MMIO_PORT3(port, \ _CNL_PORT_TX_DW7_LN0_AE, \ _CNL_PORT_TX_DW7_LN0_B, \ _CNL_PORT_TX_DW7_LN0_C, \