From patchwork Thu Jun 29 08:57:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Mahesh" X-Patchwork-Id: 9816255 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 156E76020A for ; Thu, 29 Jun 2017 08:54:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5F19528437 for ; Thu, 29 Jun 2017 08:54:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 53C242867D; Thu, 29 Jun 2017 08:54:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.7 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D94E628437 for ; Thu, 29 Jun 2017 08:54:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E98066E62B; Thu, 29 Jun 2017 08:54:30 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 608736E62A for ; Thu, 29 Jun 2017 08:54:28 +0000 (UTC) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Jun 2017 01:54:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,280,1496127600"; d="scan'208";a="280056340" Received: from unknown (HELO localhost.localdomain) ([10.223.25.241]) by fmsmga004.fm.intel.com with ESMTP; 29 Jun 2017 01:54:26 -0700 From: Mahesh Kumar To: intel-gfx@lists.freedesktop.org Date: Thu, 29 Jun 2017 14:27:39 +0530 Message-Id: <20170629085740.31588-2-mahesh1.kumar@intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170629085740.31588-1-mahesh1.kumar@intel.com> References: <20170629085740.31588-1-mahesh1.kumar@intel.com> Cc: paulo.r.zanoni@intel.com, maarten.lankhorst@intel.com Subject: [Intel-gfx] [PATCH 1/2] drm/i915/skl+: Check for supported plane configuration in Interlace mode X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP In Gen9 platform Interlaced fetch mode doesn't support following plane configuration: - Y/Yf tiling - 90/270 rotation - Scaling - YUV420 hybrid planar source pixel formats. This patch adds check to fail the flip if any of the above configuration is requested. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 4e03ca6c946f..1f2394a0c07d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11022,6 +11022,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, bool is_crtc_enabled = crtc_state->active; bool turn_off, turn_on, visible, was_visible; struct drm_framebuffer *fb = plane_state->fb; + const struct drm_display_mode *mode = &crtc_state->adjusted_mode; int ret; if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { @@ -11108,6 +11109,41 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, !needs_scaling(old_plane_state)) pipe_config->disable_lp_wm = true; + /* + * Y-tiling is not supported in IF-ID Interlace mode in + * GEN9 and above. + * Scaling is not supported with Interlaced fetch mode. + * YUV420 hybrid planar source pixel formats are not supported with + * Interlaced fetch mode. + */ + if (visible && INTEL_GEN(dev_priv) >= 9 && + mode->flags & DRM_MODE_FLAG_INTERLACE) { + struct drm_format_name_buf format_name; + + if (fb->modifier == I915_FORMAT_MOD_Y_TILED || + fb->modifier == I915_FORMAT_MOD_Yf_TILED) { + DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n"); + return -EINVAL; + } + + if (needs_scaling(to_intel_plane_state(plane_state))) { + DRM_DEBUG_KMS("Scaling not supported in IF-ID mode\n"); + return -EINVAL; + } + + switch (fb->format->format) { + case DRM_FORMAT_NV12: + case DRM_FORMAT_YUV420: + case DRM_FORMAT_YVU420: + DRM_DEBUG_KMS("Unsupported pixel format %s for IF-ID\n", + drm_get_format_name(fb->format->format, + &format_name)); + return -EINVAL; + default: + break; + } + } + return 0; }