| Message ID | 20170705143154.32132-12-mahesh1.kumar@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Mahesh Kumar schreef op wo 05-07-2017 om 20:01 [+0530]: > From: "Kumar, Mahesh" <mahesh1.kumar@intel.com> > > This patch adds IPC support for platforms. This patch enables IPC > only for BXT/KBL platform as for SKL recommendation is to keep it > disabled. CFL/CNL missing. ;-) > IPC (Isochronous Priority Control) is the hardware feature, which > dynamically controls the memory read priority of Display. > > When IPC is enabled, plane read requests are sent at high priority > until > filling above the transition watermark, then the requests are sent at > lower priority until dropping below the level 0 watermark. > The lower priority requests allow other memory clients to have better > memory access. When IPC is disabled, all plane read requests are sent > at > high priority. > > Changes since V1: > - Remove commandline parameter to disable ipc > - Address Paulo's comments > Changes since V2: > - Address review comments > - Set ipc_enabled flag > Changes since V3: > - move ipc_enabled flag assignment inside intel_ipc_enable function > Changes since V4: > - Re-enable IPC after suspend/resume > Changes since V5: > - Enable IPC for all gen >=9 except SKL > > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.c | 4 +++- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_display.c | 1 + > drivers/gpu/drm/i915/intel_drv.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++ > 5 files changed, 22 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c > b/drivers/gpu/drm/i915/i915_drv.c > index 9167a73f3c69..224e00610581 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -1334,7 +1334,7 @@ int i915_driver_load(struct pci_dev *pdev, > const struct pci_device_id *ent) > > intel_runtime_pm_enable(dev_priv); > > - dev_priv->ipc_enabled = false; > + intel_enable_ipc(dev_priv); > > if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) > DRM_INFO("DRM_I915_DEBUG enabled\n"); > @@ -2598,6 +2598,8 @@ static int intel_runtime_resume(struct device > *kdev) > if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) > intel_hpd_init(dev_priv); > > + intel_enable_ipc(dev_priv); > + > enable_rpm_wakeref_asserts(dev_priv); > > if (ret) > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > index 64cc674b652a..09af90f8cd0a 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6728,6 +6728,7 @@ enum { > #define DISP_FBC_WM_DIS (1<<15) > #define DISP_ARB_CTL2 _MMIO(0x45004) > #define DISP_DATA_PARTITION_5_6 (1<<6) > +#define DISP_IPC_ENABLE (1<<3) > #define DBUF_CTL _MMIO(0x45008) > #define DBUF_POWER_REQUEST (1<<31) > #define DBUF_POWER_STATE (1<<30) > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 0648fd74be87..e610b4395dcc 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -15723,6 +15723,7 @@ void intel_display_resume(struct drm_device > *dev) > if (!ret) > ret = __intel_display_resume(dev, state, &ctx); > > + intel_enable_ipc(dev_priv); > drm_modeset_drop_locks(&ctx); > drm_modeset_acquire_fini(&ctx); > > diff --git a/drivers/gpu/drm/i915/intel_drv.h > b/drivers/gpu/drm/i915/intel_drv.h > index d17a32437f07..d90b239bd85d 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -1883,6 +1883,7 @@ bool ilk_disable_lp_wm(struct drm_device *dev); > int sanitize_rc6_option(struct drm_i915_private *dev_priv, int > enable_rc6); > int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc, > struct intel_crtc_state *cstate); > +void intel_enable_ipc(struct drm_i915_private *dev_priv); > static inline int intel_enable_rc6(void) > { > return i915.enable_rc6; > diff --git a/drivers/gpu/drm/i915/intel_pm.c > b/drivers/gpu/drm/i915/intel_pm.c > index ad3b3d758d5c..c18695931d33 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5772,6 +5772,22 @@ void intel_update_watermarks(struct intel_crtc > *crtc) > dev_priv->display.update_wm(crtc); > } > > +void intel_enable_ipc(struct drm_i915_private *dev_priv) > +{ > + u32 val; > + > + dev_priv->ipc_enabled = false; > + if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv)) > + return; > + > + val = I915_READ(DISP_ARB_CTL2); > + > + val |= DISP_IPC_ENABLE; > + > + I915_WRITE(DISP_ARB_CTL2, val); > + dev_priv->ipc_enabled = true; > +} > + > /* > * Lock protecting IPS related data structures > */
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 9167a73f3c69..224e00610581 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1334,7 +1334,7 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent) intel_runtime_pm_enable(dev_priv); - dev_priv->ipc_enabled = false; + intel_enable_ipc(dev_priv); if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) DRM_INFO("DRM_I915_DEBUG enabled\n"); @@ -2598,6 +2598,8 @@ static int intel_runtime_resume(struct device *kdev) if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) intel_hpd_init(dev_priv); + intel_enable_ipc(dev_priv); + enable_rpm_wakeref_asserts(dev_priv); if (ret) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 64cc674b652a..09af90f8cd0a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6728,6 +6728,7 @@ enum { #define DISP_FBC_WM_DIS (1<<15) #define DISP_ARB_CTL2 _MMIO(0x45004) #define DISP_DATA_PARTITION_5_6 (1<<6) +#define DISP_IPC_ENABLE (1<<3) #define DBUF_CTL _MMIO(0x45008) #define DBUF_POWER_REQUEST (1<<31) #define DBUF_POWER_STATE (1<<30) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0648fd74be87..e610b4395dcc 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -15723,6 +15723,7 @@ void intel_display_resume(struct drm_device *dev) if (!ret) ret = __intel_display_resume(dev, state, &ctx); + intel_enable_ipc(dev_priv); drm_modeset_drop_locks(&ctx); drm_modeset_acquire_fini(&ctx); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index d17a32437f07..d90b239bd85d 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1883,6 +1883,7 @@ bool ilk_disable_lp_wm(struct drm_device *dev); int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6); int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc, struct intel_crtc_state *cstate); +void intel_enable_ipc(struct drm_i915_private *dev_priv); static inline int intel_enable_rc6(void) { return i915.enable_rc6; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ad3b3d758d5c..c18695931d33 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5772,6 +5772,22 @@ void intel_update_watermarks(struct intel_crtc *crtc) dev_priv->display.update_wm(crtc); } +void intel_enable_ipc(struct drm_i915_private *dev_priv) +{ + u32 val; + + dev_priv->ipc_enabled = false; + if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv)) + return; + + val = I915_READ(DISP_ARB_CTL2); + + val |= DISP_IPC_ENABLE; + + I915_WRITE(DISP_ARB_CTL2, val); + dev_priv->ipc_enabled = true; +} + /* * Lock protecting IPS related data structures */