From patchwork Fri Jul 14 19:38:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zanoni, Paulo R" X-Patchwork-Id: 9841585 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 97917602D8 for ; Fri, 14 Jul 2017 19:38:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 86E7A28752 for ; Fri, 14 Jul 2017 19:38:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7B007287BE; Fri, 14 Jul 2017 19:38:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 136EB28752 for ; Fri, 14 Jul 2017 19:38:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0B69B6E075; Fri, 14 Jul 2017 19:38:40 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5737B6E075 for ; Fri, 14 Jul 2017 19:38:38 +0000 (UTC) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP; 14 Jul 2017 12:38:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,359,1496127600"; d="scan'208";a="111461788" Received: from przanoni-mobl.amr.corp.intel.com ([10.254.178.253]) by orsmga002.jf.intel.com with ESMTP; 14 Jul 2017 12:38:36 -0700 From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Fri, 14 Jul 2017 16:38:22 -0300 Message-Id: <20170714193822.12121-1-paulo.r.zanoni@intel.com> X-Mailer: git-send-email 2.9.4 Cc: Paulo Zanoni , Praveen Paneri Subject: [Intel-gfx] [PATCH] drm/i915/fbc: add comments to the FBC auxiliary structs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP I wrote this code an year and a half ago and I couldn't exactly remember the main differences of these two structures when reviewing a new FBC patch. Add some comments to help explain what's the purpose of each struct. For the record, the original commits are: b183b3f14395 ("drm/i915/fbc: introduce struct intel_fbc_reg_params") aaf78d276ba0 ("drm/i915/fbc: introduce struct intel_fbc_state_cache") Cc: Praveen Paneri Signed-off-by: Paulo Zanoni Reviewed-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_drv.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a1eeb489..271402c 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1063,6 +1063,11 @@ struct intel_fbc { bool underrun_detected; struct work_struct underrun_work; + /* + * Due to the atomic rules we can't access some structures without the + * appropriate locking, so we cache information here in order to avoid + * these problems. + */ struct intel_fbc_state_cache { struct i915_vma *vma; @@ -1084,6 +1089,13 @@ struct intel_fbc { } fb; } state_cache; + /* + * This structure contains everything that's relevant to program the + * hardware registers. When we want to figure out if we need to disable + * and re-enable FBC for a new configuration we just check if there's + * something different in the struct. The genx_fbc_activate functions + * are supposed to read from it in order to program the registers. + */ struct intel_fbc_reg_params { struct i915_vma *vma;