diff mbox

[05/15] drm/i915/guc: Move Guc notification handling to separate function

Message ID 20170804162712.20468-6-michal.wajdeczko@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Michal Wajdeczko Aug. 4, 2017, 4:27 p.m. UTC 
To allow future code reuse. While here, fix comment style.

Suggested-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 33 ++-------------------------------
 drivers/gpu/drm/i915/intel_uc.c | 37 +++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_uc.h |  1 +
 3 files changed, 40 insertions(+), 31 deletions(-)

Comments

Chris Wilson Aug. 4, 2017, 6 p.m. UTC | #1 
Quoting Michal Wajdeczko (2017-08-04 17:27:02)
> To allow future code reuse. While here, fix comment style.

Might as well fix the alignment as well then... 

> +               /* Handle flush interrupt in bottom half */
> +               queue_work(dev_priv->guc.log.runtime.flush_wq,
> +                               &dev_priv->guc.log.runtime.flush_work);
> +
> +               dev_priv->guc.log.flush_interrupt_count++;
> +       } else {
> +               /*
> +                * Not clearing of unhandled event bits won't result in
> +                * re-triggering of the interrupt.
> +                */
> +       }
> +}

Argh, and those are spaces not tabs! Back to the checkpatch dungeon you
go, until you are sorry!
-Chris
Michal Wajdeczko Aug. 4, 2017, 7:35 p.m. UTC | #2 
On Fri, Aug 04, 2017 at 07:00:33PM +0100, Chris Wilson wrote:
> Quoting Michal Wajdeczko (2017-08-04 17:27:02)
> > To allow future code reuse. While here, fix comment style.
> 
> Might as well fix the alignment as well then... 
> 
> > +               /* Handle flush interrupt in bottom half */
> > +               queue_work(dev_priv->guc.log.runtime.flush_wq,
> > +                               &dev_priv->guc.log.runtime.flush_work);
> > +
> > +               dev_priv->guc.log.flush_interrupt_count++;
> > +       } else {
> > +               /*
> > +                * Not clearing of unhandled event bits won't result in
> > +                * re-triggering of the interrupt.
> > +                */
> > +       }
> > +}
> 
> Argh, and those are spaces not tabs! Back to the checkpatch dungeon you
> go, until you are sorry!

Hmm, that's weird. On my side there were all tabs.

$ scripts/checkpatch.pl ../RFC/0005-drm-i915-guc-Move-Guc-notification-handling-to-separ.patch
total: 0 errors, 0 warnings, 89 lines checked

../RFC/0005-drm-i915-guc-Move-Guc-notification-handling-to-separ.patch has no obvious style problems and is ready for submission.
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 196caa4..ac69534 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1675,37 +1675,8 @@  static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
 
 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
 {
-	if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
-		/* Sample the log buffer flush related bits & clear them out now
-		 * itself from the message identity register to minimize the
-		 * probability of losing a flush interrupt, when there are back
-		 * to back flush interrupts.
-		 * There can be a new flush interrupt, for different log buffer
-		 * type (like for ISR), whilst Host is handling one (for DPC).
-		 * Since same bit is used in message register for ISR & DPC, it
-		 * could happen that GuC sets the bit for 2nd interrupt but Host
-		 * clears out the bit on handling the 1st interrupt.
-		 */
-		u32 msg, flush;
-
-		msg = I915_READ(SOFT_SCRATCH(15));
-		flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
-			       INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER);
-		if (flush) {
-			/* Clear the message bits that are handled */
-			I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
-
-			/* Handle flush interrupt in bottom half */
-			queue_work(dev_priv->guc.log.runtime.flush_wq,
-				   &dev_priv->guc.log.runtime.flush_work);
-
-			dev_priv->guc.log.flush_interrupt_count++;
-		} else {
-			/* Not clearing of unhandled event bits won't result in
-			 * re-triggering of the interrupt.
-			 */
-		}
-	}
+	if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT)
+		intel_guc_notification_handler(&dev_priv->guc);
 }
 
 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index c704968..1e6390e 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -532,6 +532,43 @@  int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
 	return ret;
 }
 
+void intel_guc_notification_handler(struct intel_guc *guc)
+{
+	struct drm_i915_private *dev_priv = guc_to_i915(guc);
+	u32 msg, flush;
+
+	/*
+	 * Sample the log buffer flush related bits & clear them out now
+	 * itself from the message identity register to minimize the
+	 * probability of losing a flush interrupt, when there are back
+	 * to back flush interrupts.
+	 * There can be a new flush interrupt, for different log buffer
+	 * type (like for ISR), whilst Host is handling one (for DPC).
+	 * Since same bit is used in message register for ISR & DPC, it
+	 * could happen that GuC sets the bit for 2nd interrupt but Host
+	 * clears out the bit on handling the 1st interrupt.
+	 */
+
+	msg = I915_READ(SOFT_SCRATCH(15));
+	flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
+		       INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER);
+	if (flush) {
+		/* Clear the message bits that are handled */
+		I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
+
+		/* Handle flush interrupt in bottom half */
+		queue_work(dev_priv->guc.log.runtime.flush_wq,
+				&dev_priv->guc.log.runtime.flush_work);
+
+		dev_priv->guc.log.flush_interrupt_count++;
+	} else {
+		/*
+		 * Not clearing of unhandled event bits won't result in
+		 * re-triggering of the interrupt.
+		 */
+	}
+}
+
 int intel_guc_sample_forcewake(struct intel_guc *guc)
 {
 	struct drm_i915_private *dev_priv = guc_to_i915(guc);
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 9353ac3..2789179 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -226,6 +226,7 @@  void intel_uc_init_fw(struct drm_i915_private *dev_priv);
 void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
 int intel_uc_init_hw(struct drm_i915_private *dev_priv);
 void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
+void intel_guc_notification_handler(struct intel_guc *guc);
 int intel_guc_sample_forcewake(struct intel_guc *guc);
 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len, u32 *response);
 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, u32 *response);