From patchwork Tue Aug 8 12:30:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 9888027 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3525860384 for ; Tue, 8 Aug 2017 12:31:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2753A2887F for ; Tue, 8 Aug 2017 12:31:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1C56B2888E; Tue, 8 Aug 2017 12:31:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3011428889 for ; Tue, 8 Aug 2017 12:31:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 214BA6E0FF; Tue, 8 Aug 2017 12:31:01 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 22AB56E0FF for ; Tue, 8 Aug 2017 12:30:59 +0000 (UTC) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Aug 2017 05:30:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,343,1498546800"; d="scan'208";a="116883869" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga004.jf.intel.com with ESMTP; 08 Aug 2017 05:30:58 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [172.28.174.25]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id v78CUvMH011650; Tue, 8 Aug 2017 13:30:57 +0100 From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Tue, 8 Aug 2017 12:30:40 +0000 Message-Id: <20170808123040.1460-1-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20170804162712.20468-1-michal.wajdeczko@intel.com> References: <20170804162712.20468-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH v3 15/16] drm/i915/guc: Trace messages from CT while in debug X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP During debug we may want to investigate all communication from the Guc. Add proper tracing macros in debug config. v2: convert remaining DRM_DEBUG into new CT_DEBUG (Michal) v3: use dedicated Kconfig (Daniele) Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Chris Wilson Acked-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/Kconfig.debug | 12 +++++++++++ drivers/gpu/drm/i915/intel_guc_ct.c | 41 +++++++++++++++++++++++++++---------- 2 files changed, 42 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug index 78c5c04..0c20b75 100644 --- a/drivers/gpu/drm/i915/Kconfig.debug +++ b/drivers/gpu/drm/i915/Kconfig.debug @@ -73,6 +73,18 @@ config DRM_I915_SW_FENCE_CHECK_DAG If in doubt, say "N". +config DRM_I915_DEBUG_GUC + bool "Enable additional driver debugging for GuC" + depends on DRM_I915 + default n + help + Choose this option to turn on extra driver debugging that may affect + performance but will help resolve GuC related issues. + + Recommended for driver developers only. + + If in doubt, say "N". + config DRM_I915_SELFTEST bool "Enable selftests upon driver load" depends on DRM_I915 diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/gpu/drm/i915/intel_guc_ct.c index e6912be..28d7228 100644 --- a/drivers/gpu/drm/i915/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/intel_guc_ct.c @@ -24,6 +24,12 @@ #include "i915_drv.h" #include "intel_guc_ct.h" +#ifdef CONFIG_DRM_I915_DEBUG_GUC +#define CT_DEBUG_DRIVER(...) DRM_DEBUG_DRIVER(__VA_ARGS__) +#else +#define CT_DEBUG_DRIVER(...) +#endif + struct ct_request { struct list_head link; u32 fence; @@ -69,8 +75,8 @@ static inline const char *guc_ct_buffer_type_to_str(u32 type) static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc, u32 cmds_addr, u32 size, u32 owner) { - DRM_DEBUG_DRIVER("CT: desc %p init addr=%#x size=%u owner=%u\n", - desc, cmds_addr, size, owner); + CT_DEBUG_DRIVER("CT: desc %p init addr=%#x size=%u owner=%u\n", + desc, cmds_addr, size, owner); memset(desc, 0, sizeof(*desc)); desc->addr = cmds_addr; desc->size = size; @@ -79,8 +85,8 @@ static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc, static void guc_ct_buffer_desc_reset(struct guc_ct_buffer_desc *desc) { - DRM_DEBUG_DRIVER("CT: desc %p reset head=%u tail=%u\n", - desc, desc->head, desc->tail); + CT_DEBUG_DRIVER("CT: desc %p reset head=%u tail=%u\n", + desc, desc->head, desc->tail); desc->head = 0; desc->tail = 0; desc->is_in_error = 0; @@ -176,7 +182,7 @@ static int ctch_init(struct intel_guc *guc, err = PTR_ERR(blob); goto err_vma; } - DRM_DEBUG_DRIVER("CT: vma base=%#x\n", guc_ggtt_offset(ctch->vma)); + CT_DEBUG_DRIVER("CT: vma base=%#x\n", guc_ggtt_offset(ctch->vma)); /* store pointers to desc and cmds */ for (i = 0; i < ARRAY_SIZE(ctch->ctbs); i++) { @@ -190,8 +196,8 @@ static int ctch_init(struct intel_guc *guc, err_vma: i915_vma_unpin_and_release(&ctch->vma); err_out: - DRM_DEBUG_DRIVER("CT: channel %d initialization failed; err=%d\n", - ctch->owner, err); + CT_DEBUG_DRIVER("CT: channel %d initialization failed; err=%d\n", + ctch->owner, err); return err; } @@ -211,8 +217,8 @@ static int ctch_open(struct intel_guc *guc, int err; int i; - DRM_DEBUG_DRIVER("CT: channel %d reopen=%s\n", - ctch->owner, yesno(ctch_is_open(ctch))); + CT_DEBUG_DRIVER("CT: channel %d reopen=%s\n", + ctch->owner, yesno(ctch_is_open(ctch))); if (!ctch->vma) { err = ctch_init(guc, ctch); @@ -325,6 +331,10 @@ static int ctb_write(struct intel_guc_ct_buffer *ctb, (send_response ? GUC_CT_MSG_SEND_STATUS : 0) | (action[0] << GUC_CT_MSG_ACTION_SHIFT); + CT_DEBUG_DRIVER("CT: writing %*phn %*phn %*phn\n", + 4, &header, 4, &fence, + 4*(len - 1), &action[1]); + cmds[tail] = header; tail = (tail + 1) % size; @@ -500,6 +510,9 @@ static int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len, if (unlikely(ret < 0)) { DRM_ERROR("CT: send action %#X failed; err=%d status=%#X\n", action[0], ret, status); + } else if (unlikely(ret)) { + CT_DEBUG_DRIVER("CT: send action %#x returned %d (%#x)\n", + action[0], ret, ret); } mutex_unlock(&guc->send_mutex); @@ -546,10 +559,12 @@ static int ctb_read(struct intel_guc_ct_buffer *ctb, u32 *data) /* beware of buffer wrap case */ if (unlikely(available < 0)) available += size; + CT_DEBUG_DRIVER("CT: available %d (%u:%u)\n", available, head, tail); GEM_BUG_ON(available < 0); data[0] = cmds[head]; head = (head + 1) % size; + CT_DEBUG_DRIVER("CT: header %#x\n", data[0]); /* message len with header */ len = ct_header_get_len(data[0]) + 1; @@ -567,6 +582,7 @@ static int ctb_read(struct intel_guc_ct_buffer *ctb, u32 *data) data[i] = cmds[head]; head = (head + 1) % size; } + CT_DEBUG_DRIVER("CT: received %*phn\n", 4*len, data); desc->head = head * 4; return 0; @@ -592,12 +608,13 @@ static int guc_handle_response(struct intel_guc *guc, const u32 *msg) DRM_ERROR("CT: corrupted status %*phn\n", 4*len, msg); status = INTEL_GUC_STATUS_GENERIC_FAIL; } + CT_DEBUG_DRIVER("CT: response fence %u status %#x\n", fence, status); spin_lock_irqsave(&guc->ct.lock, flags); list_for_each_entry(req, &guc->ct.pending_requests, link) { if (req->fence != fence) { - DRM_DEBUG_DRIVER("CT: request %u awaits response\n", - req->fence); + CT_DEBUG_DRIVER("CT: request %u awaits response\n", + req->fence); continue; } req->response_len = len - 3; @@ -623,6 +640,7 @@ static int guc_handle_request(struct intel_guc *guc, const u32 *msg) GEM_BUG_ON(ct_header_is_response(header)); /* Request message layout beyond header is request specific */ + CT_DEBUG_DRIVER("CT: request %#x\n", ct_header_get_action(header)); request = kmalloc(sizeof(*request) + 4*len, GFP_ATOMIC); if (unlikely(!request)) { @@ -662,6 +680,7 @@ static bool guc_process_incoming_requests(struct intel_guc *guc) header = request->data[0]; action = ct_header_get_action(header); len = ct_header_get_len(header) + 1; /* also count header dw */ + CT_DEBUG_DRIVER("CT: processing request %*phn\n", 4*len, request->data); switch (action) { case INTEL_GUC_ACTION_DEFAULT: