@@ -10507,6 +10507,28 @@ connected_sink_compute_bpp(struct intel_connector *connector,
}
}
+static void
+connected_sink_max_bpp(struct intel_digital_connector_state *intel_conn_state,
+ struct intel_crtc_state *pipe_config)
+{
+ switch (intel_conn_state->max_bpc) {
+ case 8:
+ case 9:
+ pipe_config->pipe_bpp = 8*3;
+ break;
+ case 10:
+ case 11:
+ pipe_config->pipe_bpp = 10*3;
+ break;
+ case 12:
+ pipe_config->pipe_bpp = 12*3;
+ break;
+ default:
+ break;
+ }
+ DRM_DEBUG_KMS("Limiting display bpp to %d\n", pipe_config->pipe_bpp);
+}
+
static int
compute_baseline_pipe_bpp(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config)
@@ -10515,6 +10537,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
struct drm_atomic_state *state;
struct drm_connector *connector;
struct drm_connector_state *connector_state;
+ struct intel_digital_connector_state *intel_conn_state;
int bpp, i;
if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
@@ -10535,6 +10558,10 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc,
if (connector_state->crtc != &crtc->base)
continue;
+ intel_conn_state = to_intel_digital_connector_state(connector_state);
+ if (intel_conn_state->max_bpc)
+ connected_sink_max_bpp(intel_conn_state, pipe_config);
+
connected_sink_compute_bpp(to_intel_connector(connector),
pipe_config);
}