From patchwork Tue Dec 5 05:15:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sean Paul X-Patchwork-Id: 10092107 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2CD9D60329 for ; Tue, 5 Dec 2017 05:16:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1F5362868C for ; Tue, 5 Dec 2017 05:16:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 13FB728DA2; Tue, 5 Dec 2017 05:16:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id ACA262868C for ; Tue, 5 Dec 2017 05:16:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 50F646E3FC; Tue, 5 Dec 2017 05:16:01 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-yb0-x242.google.com (mail-yb0-x242.google.com [IPv6:2607:f8b0:4002:c09::242]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9856F6E3F8 for ; Tue, 5 Dec 2017 05:16:00 +0000 (UTC) Received: by mail-yb0-x242.google.com with SMTP id i15so7622538ybk.0 for ; Mon, 04 Dec 2017 21:16:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zywmNKFasqpQhvhvRQoqzJ+Q96DEK6I27hHzjGgtoMg=; b=iwvGmhynxbELo6yJvH9Zz6PTQyKUDfe2wGrxJGlCCHWW22Rbc8EzHam7EHSftbxgNb jU7s+emJufNiJUaq9divnJIcNrOZsXB1V4p9OAXTA7IdKChrc48dxVNuz4/54f3qgS2m Bzdytfl5uSN32wJX2zq3EJ7Ose5bOpbMocC2E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zywmNKFasqpQhvhvRQoqzJ+Q96DEK6I27hHzjGgtoMg=; b=cwzU/CjJANCB+hnvtMZxdX4zBaDsjt5Tj+GDPr7vD8LrlhxDUWoVq0l7YZCLDnj4wR D7Il1LYTUxvmfRq1WB8FulxEDG8HU5iM/3Q8ed5qpeTuz3Efa/1icLH5tLb3Jp2hbZhm uIyWtx3obNHWERGtFgHvFCuy+RbqopPZudUZHjKCnyxk9/+T70YXDj9ZUol80E0Kcfzj oLsXeYxUeYXcm0mlNFdXPUvYGtxTs6VvaI06WjHUwtSFfEYM/xC1Hnrlukj5LKwXS3vC gB5KGI5o7liXeFeEqV3pWbeYzdCDoiHNncwjHpVWCWkgyZo0j5ZaOi9BWt+jVXYZ3TnQ MHyw== X-Gm-Message-State: AKGB3mLF/9m58qwOXQtZAmbkYZPnXOr8jXLMULrkF7RsvyrME9BAIsb2 Rx2gKSxArWamDqpb3l9EvUy62A== X-Google-Smtp-Source: AGs4zMZ+MM4g0q/rtMsFImfSGMEXepsnKA7h8/+tUlNQXMXycCTerqjqhmlnb2QdxhSWCD1Y0e8Y1g== X-Received: by 10.37.32.138 with SMTP id g132mr6777591ybg.35.1512450959712; Mon, 04 Dec 2017 21:15:59 -0800 (PST) Received: from rosewood.cam.corp.google.com ([2620:0:1013:11:d3af:69ac:1964:28e8]) by smtp.gmail.com with ESMTPSA id z145sm2647231ywa.98.2017.12.04.21.15.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Dec 2017 21:15:59 -0800 (PST) From: Sean Paul To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Date: Tue, 5 Dec 2017 00:15:05 -0500 Message-Id: <20171205051513.8603-7-seanpaul@chromium.org> X-Mailer: git-send-email 2.15.0.531.g2ccb3012c9-goog In-Reply-To: <20171205051513.8603-1-seanpaul@chromium.org> References: <20171205051513.8603-1-seanpaul@chromium.org> MIME-Version: 1.0 Cc: seanpaul@google.com, David Airlie , linux-kernel@vger.kernel.org, Rodrigo Vivi , daniel.vetter@intel.com Subject: [Intel-gfx] [PATCH v3 6/9] drm/i915: Make use of indexed write GMBUS feature X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This patch enables the indexed write feature of the GMBUS to concatenate 2 consecutive messages into one. The criteria for an indexed write is that both messages are writes, the first is length == 1, and the second is length > 0. The first message is sent out by the GMBUS as the slave command, and the second one is sent via the GMBUS FIFO as usual. Changes in v3: - Added to series Suggested-by: Ville Syrjälä Signed-off-by: Sean Paul Reviewed-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_i2c.c | 39 ++++++++++++++++++++++++++++++++++----- 1 file changed, 34 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 49fdf09f9919..7399009aee0a 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -373,7 +373,8 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, static int gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, - unsigned short addr, u8 *buf, unsigned int len) + unsigned short addr, u8 *buf, unsigned int len, + u32 gmbus1_index) { unsigned int chunk_size = len; u32 val, loop; @@ -386,7 +387,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, I915_WRITE_FW(GMBUS3, val); I915_WRITE_FW(GMBUS1, - GMBUS_CYCLE_WAIT | + gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); @@ -409,7 +410,8 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, } static int -gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) +gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg, + u32 gmbus1_index) { u8 *buf = msg->buf; unsigned int tx_size = msg->len; @@ -419,7 +421,8 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) do { len = min(tx_size, GMBUS_BYTE_COUNT_MAX); - ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len); + ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len, + gmbus1_index); if (ret) return ret; @@ -430,6 +433,14 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) return 0; } +static int +gmbus_xfer_index_write(struct drm_i915_private *dev_priv, u8 cmd, + struct i2c_msg *msg) +{ + u8 gmbus1_index = GMBUS_CYCLE_INDEX | (cmd << GMBUS_SLAVE_INDEX_SHIFT); + return gmbus_xfer_write(dev_priv, msg, gmbus1_index); +} + /* * The gmbus controller can combine a 1 or 2 byte write with a read that * immediately follows it by using an "INDEX" cycle. @@ -444,6 +455,20 @@ gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) (msgs[i + 1].flags & I2C_M_RD)); } +/* + * The gmbus controller can combine a 2-msg write into a single write that + * immediately follows it by using an "INDEX" cycle. + */ +static bool +gmbus_is_index_write(struct i2c_msg *msgs, int i, int num) +{ + return (i + 1 < num && + msgs[i].addr == msgs[i + 1].addr && + !(msgs[i].flags & I2C_M_RD) && + !(msgs[i + 1].flags & I2C_M_RD) && + (msgs[i].len == 1 || msgs[i + 1].len > 0)); +} + static int gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) { @@ -489,10 +514,14 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) if (gmbus_is_index_read(msgs, i, num)) { ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); inc = 2; /* an index read is two msgs */ + } else if (gmbus_is_index_write(msgs, i, num)) { + ret = gmbus_xfer_index_write(dev_priv, msgs[i].buf[0], + &msgs[i + 1]); + inc = 2; /* an index write is two msgs */ } else if (msgs[i].flags & I2C_M_RD) { ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); } else { - ret = gmbus_xfer_write(dev_priv, &msgs[i]); + ret = gmbus_xfer_write(dev_priv, &msgs[i], 0); } if (!ret)