From patchwork Wed Dec 13 00:59:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dhinakaran Pandiyan X-Patchwork-Id: 10108559 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BF29860327 for ; Wed, 13 Dec 2017 00:59:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B063628D75 for ; Wed, 13 Dec 2017 00:59:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A3EF928D7C; Wed, 13 Dec 2017 00:59:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 28EB828D75 for ; Wed, 13 Dec 2017 00:59:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D473A6E283; Wed, 13 Dec 2017 00:59:46 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9BA4A6E283 for ; Wed, 13 Dec 2017 00:59:45 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Dec 2017 16:59:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,395,1508828400"; d="scan'208";a="17743806" Received: from dk-thinkpad-x260.jf.intel.com (HELO localhost.localdomain) ([10.54.75.38]) by orsmga002.jf.intel.com with ESMTP; 12 Dec 2017 16:59:44 -0800 From: Dhinakaran Pandiyan To: intel-gfx@lists.freedesktop.org Date: Tue, 12 Dec 2017 16:59:34 -0800 Message-Id: <20171213005934.7010-1-dhinakaran.pandiyan@intel.com> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 Cc: Dhinakaran Pandiyan , Rodrigo Vivi Subject: [Intel-gfx] [PATCH] drm/915/psr: Set psr.source_ok during atomic_check X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Since commit 4d90f2d507ab ("drm/i915: Start tracking PSR state in crtc state"), we check whether PSR can be enabled or not in psr_compute_config(). Given that the psr.source_ok field is supposed to track this check, set the field in psr_compute_config() as well. Now tests can distinguish between PSR not enabled due to unmet mode requirements and something going wrong during commit. Cc: Rodrigo Vivi Cc: Ville Syrjälä Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/intel_psr.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index a1ad85fa5c1a..b59a956047ff 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -358,6 +358,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, &crtc_state->base.adjusted_mode; int psr_setup_time; + dev_priv->psr.source_ok = false; + if (!HAS_PSR(dev_priv)) return; @@ -420,7 +422,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, * caps during eDP detection. */ if (!dev_priv->psr.psr2_support) { - crtc_state->has_psr = true; + dev_priv->psr.source_ok = (crtc_state->has_psr = true); return; } @@ -440,7 +442,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, return; } - crtc_state->has_psr = true; + dev_priv->psr.source_ok = (crtc_state->has_psr = true); crtc_state->has_psr2 = true; } @@ -522,8 +524,6 @@ void intel_psr_enable(struct intel_dp *intel_dp, } dev_priv->psr.psr2_support = crtc_state->has_psr2; - dev_priv->psr.source_ok = true; - dev_priv->psr.busy_frontbuffer_bits = 0; dev_priv->psr.setup_vsc(intel_dp, crtc_state); @@ -657,7 +657,7 @@ void intel_psr_disable(struct intel_dp *intel_dp, /* Disable PSR on Sink */ drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); - dev_priv->psr.enabled = NULL; + dev_priv->psr.source_ok = (dev_priv->psr.enabled = NULL); mutex_unlock(&dev_priv->psr.lock); cancel_delayed_work_sync(&dev_priv->psr.work);