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Wed, 10 Jan 2018 15:51:35 -0800 (PST) From: Anuj Phogat To: intel-gfx@lists.freedesktop.org Date: Wed, 10 Jan 2018 15:51:02 -0800 Message-Id: <20180110235102.27531-1-anuj.phogat@gmail.com> X-Mailer: git-send-email 2.13.6 Cc: Rodrigo Vivi Subject: [Intel-gfx] [PATCH libdrm] intel: Add more Coffeelake PCI IDs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Cc: Rodrigo Vivi Cc: Anusha Srivatsa Signed-off-by: Anuj Phogat Reviewed-by: Rodrigo Vivi --- intel/intel_chipset.h | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index d81b1646..3818e71e 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -223,15 +223,23 @@ #define PCI_CHIP_COFFEELAKE_S_GT1_1 0x3E90 #define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93 +#define PCI_CHIP_COFFEELAKE_S_GT1_3 0x3E99 #define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91 #define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92 #define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96 +#define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E9A #define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B #define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94 -#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5 -#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6 -#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7 -#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8 +#define PCI_CHIP_COFFEELAKE_U_GT1_1 0x3EA1 +#define PCI_CHIP_COFFEELAKE_U_GT1_2 0x3EA4 +#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA0 +#define PCI_CHIP_COFFEELAKE_U_GT2_2 0x3EA3 +#define PCI_CHIP_COFFEELAKE_U_GT2_3 0x3EA9 +#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA2 +#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA5 +#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA6 +#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7 +#define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8 #define PCI_CHIP_CANNONLAKE_U_GT2_0 0x5A52 #define PCI_CHIP_CANNONLAKE_U_GT2_1 0x5A5A @@ -477,17 +485,25 @@ #define IS_CFL_S(devid) ((devid) == PCI_CHIP_COFFEELAKE_S_GT1_1 || \ (devid) == PCI_CHIP_COFFEELAKE_S_GT1_2 || \ + (devid) == PCI_CHIP_COFFEELAKE_S_GT1_3 || \ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_1 || \ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \ - (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3) + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3 || \ + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_4) #define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \ (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2) -#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \ +#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT1_1 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT1_2 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT2_2 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT2_3 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \ - (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4) + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4 || \ + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_5) #define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \ IS_CFL_H(devid) || \