| Message ID | 20180127024923.3093-3-dhinakaran.pandiyan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Jan 26, 2018 at 06:49:17PM -0800, Dhinakaran Pandiyan wrote: > intel_edp_init_dpcd() is cluttered with PSR specific DPCD checks and > intel_dp.c is huge. Yes please! Good idea. > No functional change intended. Reviewed-by: David Weinehall <david.weinehall@linux.intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 64 +------------------------------------ > drivers/gpu/drm/i915/intel_drv.h | 1 + > drivers/gpu/drm/i915/intel_psr.c | 68 ++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 70 insertions(+), 63 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index a2e887999915..2454326690fb 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -3135,35 +3135,6 @@ intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_ > DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; > } > > -static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp) > -{ > - uint8_t psr_caps = 0; > - > - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1) > - return false; > - return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED; > -} > - > -static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) > -{ > - uint8_t dprx = 0; > - > - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, > - &dprx) != 1) > - return false; > - return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; > -} > - > -static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) > -{ > - uint8_t alpm_caps = 0; > - > - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, > - &alpm_caps) != 1) > - return false; > - return alpm_caps & DP_ALPM_CAP; > -} > - > /* These are source-specific values. */ > uint8_t > intel_dp_voltage_max(struct intel_dp *intel_dp) > @@ -3714,40 +3685,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) > dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] & > DP_NO_AUX_HANDSHAKE_LINK_TRAINING; > > - /* Check if the panel supports PSR */ > - drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, > - intel_dp->psr_dpcd, > - sizeof(intel_dp->psr_dpcd)); > - if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { > - dev_priv->psr.sink_support = true; > - DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); > - } > - > - if (INTEL_GEN(dev_priv) >= 9 && > - (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { > - uint8_t frame_sync_cap; > - > - dev_priv->psr.sink_support = true; > - if (drm_dp_dpcd_readb(&intel_dp->aux, > - DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, > - &frame_sync_cap) != 1) > - frame_sync_cap = 0; > - dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; > - /* PSR2 needs frame sync as well */ > - dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; > - DRM_DEBUG_KMS("PSR2 %s on sink", > - dev_priv->psr.psr2_support ? "supported" : "not supported"); > - > - if (dev_priv->psr.psr2_support) { > - dev_priv->psr.y_cord_support = > - intel_dp_get_y_cord_status(intel_dp); > - dev_priv->psr.colorimetry_support = > - intel_dp_get_colorimetry_status(intel_dp); > - dev_priv->psr.alpm = > - intel_dp_get_alpm_status(intel_dp); > - } > - > - } > + intel_psr_init_dpcd(intel_dp); > > /* > * Read the eDP display control registers. > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 3cee54bc0352..a340bc04dad8 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -1851,6 +1851,7 @@ bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port); > > /* intel_psr.c */ > #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support) > +void intel_psr_init_dpcd(struct intel_dp *intel_dp); > void intel_psr_enable(struct intel_dp *intel_dp, > const struct intel_crtc_state *crtc_state); > void intel_psr_disable(struct intel_dp *intel_dp, > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index c12af1118647..a1b878449e83 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -56,6 +56,74 @@ > #include "intel_drv.h" > #include "i915_drv.h" > > +static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp) > +{ > + uint8_t psr_caps = 0; > + > + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1) > + return false; > + return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED; > +} > + > +static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) > +{ > + uint8_t dprx = 0; > + > + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, > + &dprx) != 1) > + return false; > + return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; > +} > + > +static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) > +{ > + uint8_t alpm_caps = 0; > + > + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, > + &alpm_caps) != 1) > + return false; > + return alpm_caps & DP_ALPM_CAP; > +} > + > +void intel_psr_init_dpcd(struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *dev_priv = > + to_i915(dp_to_dig_port(intel_dp)->base.base.dev); > + > + drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, > + sizeof(intel_dp->psr_dpcd)); > + > + if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { > + dev_priv->psr.sink_support = true; > + DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); > + } > + > + if (INTEL_GEN(dev_priv) >= 9 && > + (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { > + uint8_t frame_sync_cap; > + > + dev_priv->psr.sink_support = true; > + if (drm_dp_dpcd_readb(&intel_dp->aux, > + DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, > + &frame_sync_cap) != 1) > + frame_sync_cap = 0; > + dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; > + /* PSR2 needs frame sync as well */ > + dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; > + DRM_DEBUG_KMS("PSR2 %s on sink", > + dev_priv->psr.psr2_support ? "supported" : "not supported"); > + > + if (dev_priv->psr.psr2_support) { > + dev_priv->psr.y_cord_support = > + intel_dp_get_y_cord_status(intel_dp); > + dev_priv->psr.colorimetry_support = > + intel_dp_get_colorimetry_status(intel_dp); > + dev_priv->psr.alpm = > + intel_dp_get_alpm_status(intel_dp); > + } > + } > +} > + > static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe) > { > struct drm_i915_private *dev_priv = to_i915(dev); > -- > 2.14.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Wed, Jan 31, 2018 at 10:38:24AM +0000, David Weinehall wrote: > On Fri, Jan 26, 2018 at 06:49:17PM -0800, Dhinakaran Pandiyan wrote: > > intel_edp_init_dpcd() is cluttered with PSR specific DPCD checks and > > intel_dp.c is huge. > > Yes please! Good idea. > > > No functional change intended. > > Reviewed-by: David Weinehall <david.weinehall@linux.intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > --- > > drivers/gpu/drm/i915/intel_dp.c | 64 +------------------------------------ > > drivers/gpu/drm/i915/intel_drv.h | 1 + > > drivers/gpu/drm/i915/intel_psr.c | 68 ++++++++++++++++++++++++++++++++++++++++ > > 3 files changed, 70 insertions(+), 63 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > > index a2e887999915..2454326690fb 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -3135,35 +3135,6 @@ intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_ > > DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; > > } > > > > -static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp) > > -{ > > - uint8_t psr_caps = 0; > > - > > - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1) > > - return false; > > - return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED; > > -} > > - > > -static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) > > -{ > > - uint8_t dprx = 0; > > - > > - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, > > - &dprx) != 1) > > - return false; > > - return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; > > -} > > - > > -static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) > > -{ > > - uint8_t alpm_caps = 0; > > - > > - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, > > - &alpm_caps) != 1) > > - return false; > > - return alpm_caps & DP_ALPM_CAP; > > -} > > - > > /* These are source-specific values. */ > > uint8_t > > intel_dp_voltage_max(struct intel_dp *intel_dp) > > @@ -3714,40 +3685,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) > > dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] & > > DP_NO_AUX_HANDSHAKE_LINK_TRAINING; > > > > - /* Check if the panel supports PSR */ > > - drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, > > - intel_dp->psr_dpcd, > > - sizeof(intel_dp->psr_dpcd)); > > - if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { > > - dev_priv->psr.sink_support = true; > > - DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); > > - } > > - > > - if (INTEL_GEN(dev_priv) >= 9 && > > - (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { > > - uint8_t frame_sync_cap; > > - > > - dev_priv->psr.sink_support = true; > > - if (drm_dp_dpcd_readb(&intel_dp->aux, > > - DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, > > - &frame_sync_cap) != 1) > > - frame_sync_cap = 0; > > - dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; > > - /* PSR2 needs frame sync as well */ > > - dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; > > - DRM_DEBUG_KMS("PSR2 %s on sink", > > - dev_priv->psr.psr2_support ? "supported" : "not supported"); > > - > > - if (dev_priv->psr.psr2_support) { > > - dev_priv->psr.y_cord_support = > > - intel_dp_get_y_cord_status(intel_dp); > > - dev_priv->psr.colorimetry_support = > > - intel_dp_get_colorimetry_status(intel_dp); > > - dev_priv->psr.alpm = > > - intel_dp_get_alpm_status(intel_dp); > > - } > > - > > - } > > + intel_psr_init_dpcd(intel_dp); > > > > /* > > * Read the eDP display control registers. > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > > index 3cee54bc0352..a340bc04dad8 100644 > > --- a/drivers/gpu/drm/i915/intel_drv.h > > +++ b/drivers/gpu/drm/i915/intel_drv.h > > @@ -1851,6 +1851,7 @@ bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port); > > > > /* intel_psr.c */ > > #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support) > > +void intel_psr_init_dpcd(struct intel_dp *intel_dp); > > void intel_psr_enable(struct intel_dp *intel_dp, > > const struct intel_crtc_state *crtc_state); > > void intel_psr_disable(struct intel_dp *intel_dp, > > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > > index c12af1118647..a1b878449e83 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -56,6 +56,74 @@ > > #include "intel_drv.h" > > #include "i915_drv.h" > > > > +static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp) > > +{ > > + uint8_t psr_caps = 0; > > + > > + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1) > > + return false; > > + return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED; > > +} > > + > > +static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) > > +{ > > + uint8_t dprx = 0; > > + > > + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, > > + &dprx) != 1) > > + return false; > > + return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; > > +} > > + > > +static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) > > +{ > > + uint8_t alpm_caps = 0; > > + > > + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, > > + &alpm_caps) != 1) > > + return false; > > + return alpm_caps & DP_ALPM_CAP; > > +} > > + > > +void intel_psr_init_dpcd(struct intel_dp *intel_dp) > > +{ > > + struct drm_i915_private *dev_priv = > > + to_i915(dp_to_dig_port(intel_dp)->base.base.dev); > > + > > + drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, > > + sizeof(intel_dp->psr_dpcd)); > > + > > + if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { > > + dev_priv->psr.sink_support = true; > > + DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); > > + } > > + > > + if (INTEL_GEN(dev_priv) >= 9 && > > + (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { > > + uint8_t frame_sync_cap; > > + > > + dev_priv->psr.sink_support = true; > > + if (drm_dp_dpcd_readb(&intel_dp->aux, > > + DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, > > + &frame_sync_cap) != 1) > > + frame_sync_cap = 0; > > + dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; > > + /* PSR2 needs frame sync as well */ > > + dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; > > + DRM_DEBUG_KMS("PSR2 %s on sink", > > + dev_priv->psr.psr2_support ? "supported" : "not supported"); > > + > > + if (dev_priv->psr.psr2_support) { > > + dev_priv->psr.y_cord_support = > > + intel_dp_get_y_cord_status(intel_dp); > > + dev_priv->psr.colorimetry_support = > > + intel_dp_get_colorimetry_status(intel_dp); > > + dev_priv->psr.alpm = > > + intel_dp_get_alpm_status(intel_dp); > > + } > > + } > > +} > > + > > static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe) > > { > > struct drm_i915_private *dev_priv = to_i915(dev); > > -- > > 2.14.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index a2e887999915..2454326690fb 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3135,35 +3135,6 @@ intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_ DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; } -static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp) -{ - uint8_t psr_caps = 0; - - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1) - return false; - return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED; -} - -static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) -{ - uint8_t dprx = 0; - - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, - &dprx) != 1) - return false; - return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; -} - -static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) -{ - uint8_t alpm_caps = 0; - - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, - &alpm_caps) != 1) - return false; - return alpm_caps & DP_ALPM_CAP; -} - /* These are source-specific values. */ uint8_t intel_dp_voltage_max(struct intel_dp *intel_dp) @@ -3714,40 +3685,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING; - /* Check if the panel supports PSR */ - drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, - intel_dp->psr_dpcd, - sizeof(intel_dp->psr_dpcd)); - if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { - dev_priv->psr.sink_support = true; - DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); - } - - if (INTEL_GEN(dev_priv) >= 9 && - (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { - uint8_t frame_sync_cap; - - dev_priv->psr.sink_support = true; - if (drm_dp_dpcd_readb(&intel_dp->aux, - DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, - &frame_sync_cap) != 1) - frame_sync_cap = 0; - dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; - /* PSR2 needs frame sync as well */ - dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; - DRM_DEBUG_KMS("PSR2 %s on sink", - dev_priv->psr.psr2_support ? "supported" : "not supported"); - - if (dev_priv->psr.psr2_support) { - dev_priv->psr.y_cord_support = - intel_dp_get_y_cord_status(intel_dp); - dev_priv->psr.colorimetry_support = - intel_dp_get_colorimetry_status(intel_dp); - dev_priv->psr.alpm = - intel_dp_get_alpm_status(intel_dp); - } - - } + intel_psr_init_dpcd(intel_dp); /* * Read the eDP display control registers. diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 3cee54bc0352..a340bc04dad8 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1851,6 +1851,7 @@ bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port); /* intel_psr.c */ #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support) +void intel_psr_init_dpcd(struct intel_dp *intel_dp); void intel_psr_enable(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); void intel_psr_disable(struct intel_dp *intel_dp, diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index c12af1118647..a1b878449e83 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -56,6 +56,74 @@ #include "intel_drv.h" #include "i915_drv.h" +static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp) +{ + uint8_t psr_caps = 0; + + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1) + return false; + return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED; +} + +static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) +{ + uint8_t dprx = 0; + + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, + &dprx) != 1) + return false; + return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; +} + +static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) +{ + uint8_t alpm_caps = 0; + + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, + &alpm_caps) != 1) + return false; + return alpm_caps & DP_ALPM_CAP; +} + +void intel_psr_init_dpcd(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = + to_i915(dp_to_dig_port(intel_dp)->base.base.dev); + + drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, + sizeof(intel_dp->psr_dpcd)); + + if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { + dev_priv->psr.sink_support = true; + DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); + } + + if (INTEL_GEN(dev_priv) >= 9 && + (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { + uint8_t frame_sync_cap; + + dev_priv->psr.sink_support = true; + if (drm_dp_dpcd_readb(&intel_dp->aux, + DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, + &frame_sync_cap) != 1) + frame_sync_cap = 0; + dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; + /* PSR2 needs frame sync as well */ + dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; + DRM_DEBUG_KMS("PSR2 %s on sink", + dev_priv->psr.psr2_support ? "supported" : "not supported"); + + if (dev_priv->psr.psr2_support) { + dev_priv->psr.y_cord_support = + intel_dp_get_y_cord_status(intel_dp); + dev_priv->psr.colorimetry_support = + intel_dp_get_colorimetry_status(intel_dp); + dev_priv->psr.alpm = + intel_dp_get_alpm_status(intel_dp); + } + } +} + static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe) { struct drm_i915_private *dev_priv = to_i915(dev);
intel_edp_init_dpcd() is cluttered with PSR specific DPCD checks and intel_dp.c is huge. No functional change intended. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 64 +------------------------------------ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_psr.c | 68 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 70 insertions(+), 63 deletions(-)