@@ -8493,6 +8493,11 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
CNP_PWM_CGE_GATING_DISABLE);
}
+static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+
+}
+
static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
{
u32 val;
@@ -9003,7 +9008,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
*/
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_CANNONLAKE(dev_priv))
+ if (IS_ICELAKE(dev_priv))
+ dev_priv->display.init_clock_gating = icl_init_clock_gating;
+ else if (IS_CANNONLAKE(dev_priv))
dev_priv->display.init_clock_gating = cnl_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv))
dev_priv->display.init_clock_gating = cfl_init_clock_gating;