| Message ID | 20180213214613.3936-1-dhinakaran.pandiyan@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Quoting Dhinakaran Pandiyan (2018-02-13 21:46:13) > DRM_IOCTL_MODE_CURSOR results in a frontbuffer flush before the cursor > plane MMIOs are written to. But this flush is not necessary for PSR as > hardware tracking takes care of exiting PSR when the MMIO's are written. > > Introduce a new fb_op_origin enum to differentiate flushes due to a BO > being pinned from those originating due to a dirty fbdev buffer. Now, this > enum can be ignored in psr_flush and psr_invalidate. > > v2: Update comment in i915_gem_object_pin_to_display_plane. (Chris) > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/i915_gem.c | 11 +++++++++-- > drivers/gpu/drm/i915/intel_psr.c | 6 ++++-- > 3 files changed, 14 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 81886b74c750..3bf6c6ec0509 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -637,6 +637,7 @@ enum fb_op_origin { > ORIGIN_CS, > ORIGIN_FLIP, > ORIGIN_DIRTYFB, > + ORIGIN_PINNEDFB, > }; > > struct intel_fbc { > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index fc68b35854df..405acf3562de 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -4139,9 +4139,16 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, > > vma->display_alignment = max_t(u64, vma->display_alignment, alignment); > > - /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */ > + /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() to > + * flush the caches. > + */ > __i915_gem_object_flush_for_display(obj); > - intel_fb_obj_flush(obj, ORIGIN_DIRTYFB); > + > + /* Features like PSR might want to rely on HW to do the frontbuffer > + * flush, pass origin as ORIGIN_PINNEDFB rather than ORIGIN_DIRTYFB > + * so that their flush implementations can handle it accordingly. > + */ So why it is different? Why can't the dirtyfb ioctl benefit from HW, which the application is meant to call every frame to *all* dirty framebuffers (which include cursors in atomic)? > + intel_fb_obj_flush(obj, ORIGIN_PINNEDFB);
On Tue, 2018-02-13 at 21:54 +0000, Chris Wilson wrote: > Quoting Dhinakaran Pandiyan (2018-02-13 21:46:13) > > DRM_IOCTL_MODE_CURSOR results in a frontbuffer flush before the cursor > > plane MMIOs are written to. But this flush is not necessary for PSR as > > hardware tracking takes care of exiting PSR when the MMIO's are written. > > > > Introduce a new fb_op_origin enum to differentiate flushes due to a BO > > being pinned from those originating due to a dirty fbdev buffer. Now, this > > enum can be ignored in psr_flush and psr_invalidate. > > > > v2: Update comment in i915_gem_object_pin_to_display_plane. (Chris) > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > --- > > drivers/gpu/drm/i915/i915_drv.h | 1 + > > drivers/gpu/drm/i915/i915_gem.c | 11 +++++++++-- > > drivers/gpu/drm/i915/intel_psr.c | 6 ++++-- > > 3 files changed, 14 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > index 81886b74c750..3bf6c6ec0509 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -637,6 +637,7 @@ enum fb_op_origin { > > ORIGIN_CS, > > ORIGIN_FLIP, > > ORIGIN_DIRTYFB, > > + ORIGIN_PINNEDFB, > > }; > > > > struct intel_fbc { > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > > index fc68b35854df..405acf3562de 100644 > > --- a/drivers/gpu/drm/i915/i915_gem.c > > +++ b/drivers/gpu/drm/i915/i915_gem.c > > @@ -4139,9 +4139,16 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, > > > > vma->display_alignment = max_t(u64, vma->display_alignment, alignment); > > > > - /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */ > > + /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() to > > + * flush the caches. > > + */ > > __i915_gem_object_flush_for_display(obj); > > - intel_fb_obj_flush(obj, ORIGIN_DIRTYFB); > > + > > + /* Features like PSR might want to rely on HW to do the frontbuffer > > + * flush, pass origin as ORIGIN_PINNEDFB rather than ORIGIN_DIRTYFB > > + * so that their flush implementations can handle it accordingly. > > + */ > > So why it is different? Why can't the dirtyfb ioctl benefit from HW, which the > application is meant to call every frame to *all* dirty framebuffers > (which include cursors in atomic)? > Because the hardware requires a write to one of the pipe registers. When applications write to the buffer via fbdev, it doesn't lead to pipe MMIO write and hence does not benefit from HW triggered PSR exit. > > + intel_fb_obj_flush(obj, ORIGIN_PINNEDFB); > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoting Pandiyan, Dhinakaran (2018-02-13 22:10:48) > > > > On Tue, 2018-02-13 at 21:54 +0000, Chris Wilson wrote: > > Quoting Dhinakaran Pandiyan (2018-02-13 21:46:13) > > > DRM_IOCTL_MODE_CURSOR results in a frontbuffer flush before the cursor > > > plane MMIOs are written to. But this flush is not necessary for PSR as > > > hardware tracking takes care of exiting PSR when the MMIO's are written. > > > > > > Introduce a new fb_op_origin enum to differentiate flushes due to a BO > > > being pinned from those originating due to a dirty fbdev buffer. Now, this > > > enum can be ignored in psr_flush and psr_invalidate. > > > > > > v2: Update comment in i915_gem_object_pin_to_display_plane. (Chris) > > > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > > > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > > --- > > > drivers/gpu/drm/i915/i915_drv.h | 1 + > > > drivers/gpu/drm/i915/i915_gem.c | 11 +++++++++-- > > > drivers/gpu/drm/i915/intel_psr.c | 6 ++++-- > > > 3 files changed, 14 insertions(+), 4 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > > index 81886b74c750..3bf6c6ec0509 100644 > > > --- a/drivers/gpu/drm/i915/i915_drv.h > > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > > @@ -637,6 +637,7 @@ enum fb_op_origin { > > > ORIGIN_CS, > > > ORIGIN_FLIP, > > > ORIGIN_DIRTYFB, > > > + ORIGIN_PINNEDFB, > > > }; > > > > > > struct intel_fbc { > > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > > > index fc68b35854df..405acf3562de 100644 > > > --- a/drivers/gpu/drm/i915/i915_gem.c > > > +++ b/drivers/gpu/drm/i915/i915_gem.c > > > @@ -4139,9 +4139,16 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, > > > > > > vma->display_alignment = max_t(u64, vma->display_alignment, alignment); > > > > > > - /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */ > > > + /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() to > > > + * flush the caches. > > > + */ > > > __i915_gem_object_flush_for_display(obj); > > > - intel_fb_obj_flush(obj, ORIGIN_DIRTYFB); > > > + > > > + /* Features like PSR might want to rely on HW to do the frontbuffer > > > + * flush, pass origin as ORIGIN_PINNEDFB rather than ORIGIN_DIRTYFB > > > + * so that their flush implementations can handle it accordingly. > > > + */ > > > > So why it is different? Why can't the dirtyfb ioctl benefit from HW, which the > > application is meant to call every frame to *all* dirty framebuffers > > (which include cursors in atomic)? > > > > Because the hardware requires a write to one of the pipe registers. When > applications write to the buffer via fbdev, it doesn't lead to pipe MMIO > write and hence does not benefit from HW triggered PSR exit. Somewhere you have to have that explanation, that you rely on a subsequent mmioflip of the framebuffer to trigger the frontbuffer flush. That probably also deserves lifting out of pin_to_display_plane as currently there's no requirement that pin_to_display is followed by a flip. -Chris
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 81886b74c750..3bf6c6ec0509 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -637,6 +637,7 @@ enum fb_op_origin { ORIGIN_CS, ORIGIN_FLIP, ORIGIN_DIRTYFB, + ORIGIN_PINNEDFB, }; struct intel_fbc { diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index fc68b35854df..405acf3562de 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4139,9 +4139,16 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, vma->display_alignment = max_t(u64, vma->display_alignment, alignment); - /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */ + /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() to + * flush the caches. + */ __i915_gem_object_flush_for_display(obj); - intel_fb_obj_flush(obj, ORIGIN_DIRTYFB); + + /* Features like PSR might want to rely on HW to do the frontbuffer + * flush, pass origin as ORIGIN_PINNEDFB rather than ORIGIN_DIRTYFB + * so that their flush implementations can handle it accordingly. + */ + intel_fb_obj_flush(obj, ORIGIN_PINNEDFB); /* It should now be out of any other write domains, and we can update * the domain values for our changes. diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 2a31c7cbdb41..ddfabdff3dea 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -842,7 +842,8 @@ void intel_psr_invalidate(struct drm_i915_private *dev_priv, if (!CAN_PSR(dev_priv)) return; - if (dev_priv->psr.has_hw_tracking && origin == ORIGIN_FLIP) + if (dev_priv->psr.has_hw_tracking && + (origin == ORIGIN_FLIP || origin == ORIGIN_PINNEDFB)) return; mutex_lock(&dev_priv->psr.lock); @@ -885,7 +886,8 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, if (!CAN_PSR(dev_priv)) return; - if (dev_priv->psr.has_hw_tracking && origin == ORIGIN_FLIP) + if (dev_priv->psr.has_hw_tracking && + (origin == ORIGIN_FLIP || origin == ORIGIN_PINNEDFB)) return; mutex_lock(&dev_priv->psr.lock);
DRM_IOCTL_MODE_CURSOR results in a frontbuffer flush before the cursor plane MMIOs are written to. But this flush is not necessary for PSR as hardware tracking takes care of exiting PSR when the MMIO's are written. Introduce a new fb_op_origin enum to differentiate flushes due to a BO being pinned from those originating due to a dirty fbdev buffer. Now, this enum can be ignored in psr_flush and psr_invalidate. v2: Update comment in i915_gem_object_pin_to_display_plane. (Chris) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem.c | 11 +++++++++-- drivers/gpu/drm/i915/intel_psr.c | 6 ++++-- 3 files changed, 14 insertions(+), 4 deletions(-)