From patchwork Sat Feb 24 01:51:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 10240147 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 594866056E for ; Sat, 24 Feb 2018 01:53:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 494B729A3B for ; Sat, 24 Feb 2018 01:53:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3DC6429ACA; Sat, 24 Feb 2018 01:53:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A4C4229A3B for ; Sat, 24 Feb 2018 01:53:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AA24C6F39B; Sat, 24 Feb 2018 01:53:23 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0727D6F39A for ; Sat, 24 Feb 2018 01:53:21 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Feb 2018 17:53:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.47,385,1515484800"; d="scan'208";a="29395251" Received: from josouza-mobl.jf.intel.com ([10.24.11.40]) by FMSMGA003.fm.intel.com with ESMTP; 23 Feb 2018 17:53:21 -0800 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= To: intel-gfx@lists.freedesktop.org Date: Fri, 23 Feb 2018 17:51:40 -0800 Message-Id: <20180224015140.13803-2-jose.souza@intel.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180224015140.13803-1-jose.souza@intel.com> References: <20180224015140.13803-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/1] drm/i915/skl+: Add and enable DP AUX CH mutex X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dhinakaran Pandiyan , Rodrigo Vivi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it self, so lets use the mutex register that is available in gen9+ to avoid concurrent access by hardware and driver. Older gen handling will be done separated. Reference: https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol12-display.pdf Page 198 - AUX programming sequence Cc: Rodrigo Vivi Cc: Jani Nikula Cc: Dhinakaran Pandiyan Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 9 ++++++ drivers/gpu/drm/i915/intel_dp.c | 67 ++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 1 + 3 files changed, 77 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index eea5b2c537d4..f36e839b4b4f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5385,6 +5385,15 @@ enum { #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) +#define _DPA_AUX_CH_MUTEX (dev_priv->info.display_mmio_offset + 0x6402C) +#define _DPB_AUX_CH_MUTEX (dev_priv->info.display_mmio_offset + 0x6412C) +#define _DPC_AUX_CH_MUTEX (dev_priv->info.display_mmio_offset + 0x6422C) +#define _DPD_AUX_CH_MUTEX (dev_priv->info.display_mmio_offset + 0x6432C) +#define _DPF_AUX_CH_MUTEX (dev_priv->info.display_mmio_offset + 0x6452C) +#define DP_AUX_CH_MUTEX(port) _MMIO_PORT(port, _DPA_AUX_CH_MUTEX, _DPB_AUX_CH_MUTEX) +#define DP_AUX_CH_MUTEX_ENABLE (1 << 31) +#define DP_AUX_CH_MUTEX_STATUS (1 << 30) + /* * Computing GMCH M and N values for the Display Port link * diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 2c3eb90b9499..7be2fec51651 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1081,6 +1081,45 @@ static uint32_t intel_dp_get_aux_send_ctl(struct intel_dp *intel_dp, aux_clock_divider); } +static bool intel_dp_aux_ch_trylock(struct intel_dp *intel_dp) +{ + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *dev_priv = + to_i915(intel_dig_port->base.base.dev); + i915_reg_t ch_mutex; + + if (!intel_dp->aux_ch_mutex_reg) + return true; + + ch_mutex = intel_dp->aux_ch_mutex_reg(intel_dp); + I915_WRITE(ch_mutex, DP_AUX_CH_MUTEX_ENABLE); + + /* Spec says that mutex is acquired when status bit is read as unset, + * here waiting for 2msec or 4 tries before give up. + */ + if (intel_wait_for_register(dev_priv, ch_mutex, DP_AUX_CH_MUTEX_STATUS, + 0, 2)) { + DRM_WARN("dp_aux_ch port locked for too long"); + return false; + } + + return true; +} + +static void intel_dp_aux_ch_unlock(struct intel_dp *intel_dp) +{ + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *dev_priv = + to_i915(intel_dig_port->base.base.dev); + + if (!intel_dp->aux_ch_mutex_reg) + return; + + /* setting the status bit releases the mutex + keep mutex enabled */ + I915_WRITE(intel_dp->aux_ch_mutex_reg(intel_dp), + DP_AUX_CH_MUTEX_ENABLE | DP_AUX_CH_MUTEX_STATUS); +} + static int intel_dp_aux_ch(struct intel_dp *intel_dp, const uint8_t *send, int send_bytes, @@ -1119,6 +1158,11 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, intel_dp_check_edp(intel_dp); + if (!intel_dp_aux_ch_trylock(intel_dp)) { + ret = -EBUSY; + goto out_locked; + } + /* Try to wait for any previous AUX channel activity */ for (try = 0; try < 3; try++) { status = I915_READ_NOTRACE(ch_ctl); @@ -1248,6 +1292,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, ret = recv_bytes; out: + intel_dp_aux_ch_unlock(intel_dp); +out_locked: pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); if (vdd) @@ -1504,6 +1550,24 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) } } +static i915_reg_t skl_aux_mutex_reg(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); + enum aux_ch aux_ch = intel_dp->aux_ch; + + switch (aux_ch) { + case AUX_CH_A: + case AUX_CH_B: + case AUX_CH_C: + case AUX_CH_D: + case AUX_CH_F: + return DP_AUX_CH_MUTEX(aux_ch); + default: + MISSING_CASE(aux_ch); + return DP_AUX_CH_MUTEX(AUX_CH_A); + } +} + static void intel_dp_aux_fini(struct intel_dp *intel_dp) { @@ -1544,6 +1608,9 @@ intel_dp_aux_init(struct intel_dp *intel_dp) else intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; + if (INTEL_GEN(dev_priv) >= 9) + intel_dp->aux_ch_mutex_reg = skl_aux_mutex_reg; + drm_dp_aux_init(&intel_dp->aux); /* Failure to allocate our preferred name is not critical */ diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 8f38e584d375..267cc6c5a89f 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1128,6 +1128,7 @@ struct intel_dp { i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp); i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index); + i915_reg_t (*aux_ch_mutex_reg)(struct intel_dp *dp); /* This is called before a link training is starterd */ void (*prepare_link_retrain)(struct intel_dp *intel_dp);