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[v3,2/2] drm/i915/cnl: Kill _MMIO_PORT6 macro

Message ID 20180313041622.5718-3-mahesh1.kumar@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Kumar, Mahesh March 13, 2018, 4:16 a.m. UTC 
This patch replaces use of remaining _MMIO_PORT6 macro and removes the
macro.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

Comments

Rodrigo Vivi March 13, 2018, 8:44 p.m. UTC | #1 
On Tue, Mar 13, 2018 at 09:46:22AM +0530, Mahesh Kumar wrote:
> This patch replaces use of remaining _MMIO_PORT6 macro and removes the
> macro.
> 
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Sorry, but I noticed one more thing here :(

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 12 +++++-------
>  1 file changed, 5 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 98268163cb83..9d5afcffe641 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -153,9 +153,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
>  #define _PLL(pll, a, b) ((a) + (pll)*((b)-(a)))
>  #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
> -#define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f))
> -#define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f)			\
> -	_MMIO(_PICK(port, a0, b, c, d, e, f) + (ln * (a1 - a0)))

I had to go back and forth here so I noticed this removal of LN belongs to the
first patch.

With this moved:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

for both patches.

>  #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
>  #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
>  
> @@ -1948,20 +1945,21 @@ enum i915_power_well_id {
>  #define _CNL_PORT_PCS_DW1_LN0_C		0x162C04
>  #define _CNL_PORT_PCS_DW1_LN0_D		0x162E04
>  #define _CNL_PORT_PCS_DW1_LN0_F		0x162804
> -#define CNL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT6(port, \
> +#define CNL_PORT_PCS_DW1_GRP(port)	_MMIO(_PICK(port, \
>  						    _CNL_PORT_PCS_DW1_GRP_AE, \
>  						    _CNL_PORT_PCS_DW1_GRP_B, \
>  						    _CNL_PORT_PCS_DW1_GRP_C, \
>  						    _CNL_PORT_PCS_DW1_GRP_D, \
>  						    _CNL_PORT_PCS_DW1_GRP_AE, \
> -						    _CNL_PORT_PCS_DW1_GRP_F)
> -#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT6(port, \
> +						    _CNL_PORT_PCS_DW1_GRP_F))
> +
> +#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO(_PICK(port, \
>  						    _CNL_PORT_PCS_DW1_LN0_AE, \
>  						    _CNL_PORT_PCS_DW1_LN0_B, \
>  						    _CNL_PORT_PCS_DW1_LN0_C, \
>  						    _CNL_PORT_PCS_DW1_LN0_D, \
>  						    _CNL_PORT_PCS_DW1_LN0_AE, \
> -						    _CNL_PORT_PCS_DW1_LN0_F)
> +						    _CNL_PORT_PCS_DW1_LN0_F))
>  #define   COMMON_KEEPER_EN		(1 << 26)
>  
>  /* CNL Port TX registers */
> -- 
> 2.14.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 98268163cb83..9d5afcffe641 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -153,9 +153,6 @@  static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
 #define _PLL(pll, a, b) ((a) + (pll)*((b)-(a)))
 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
-#define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f))
-#define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f)			\
-	_MMIO(_PICK(port, a0, b, c, d, e, f) + (ln * (a1 - a0)))
 #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)
 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
 
@@ -1948,20 +1945,21 @@  enum i915_power_well_id {
 #define _CNL_PORT_PCS_DW1_LN0_C		0x162C04
 #define _CNL_PORT_PCS_DW1_LN0_D		0x162E04
 #define _CNL_PORT_PCS_DW1_LN0_F		0x162804
-#define CNL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT6(port, \
+#define CNL_PORT_PCS_DW1_GRP(port)	_MMIO(_PICK(port, \
 						    _CNL_PORT_PCS_DW1_GRP_AE, \
 						    _CNL_PORT_PCS_DW1_GRP_B, \
 						    _CNL_PORT_PCS_DW1_GRP_C, \
 						    _CNL_PORT_PCS_DW1_GRP_D, \
 						    _CNL_PORT_PCS_DW1_GRP_AE, \
-						    _CNL_PORT_PCS_DW1_GRP_F)
-#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT6(port, \
+						    _CNL_PORT_PCS_DW1_GRP_F))
+
+#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO(_PICK(port, \
 						    _CNL_PORT_PCS_DW1_LN0_AE, \
 						    _CNL_PORT_PCS_DW1_LN0_B, \
 						    _CNL_PORT_PCS_DW1_LN0_C, \
 						    _CNL_PORT_PCS_DW1_LN0_D, \
 						    _CNL_PORT_PCS_DW1_LN0_AE, \
-						    _CNL_PORT_PCS_DW1_LN0_F)
+						    _CNL_PORT_PCS_DW1_LN0_F))
 #define   COMMON_KEEPER_EN		(1 << 26)
 
 /* CNL Port TX registers */