From patchwork Fri Mar 16 12:14:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 10287017 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A3D1A601A0 for ; Fri, 16 Mar 2018 12:15:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9413928E28 for ; Fri, 16 Mar 2018 12:15:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 88BD528E2C; Fri, 16 Mar 2018 12:15:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C286028E28 for ; Fri, 16 Mar 2018 12:15:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2C7CD6EB38; Fri, 16 Mar 2018 12:15:20 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7EC5A6EB37 for ; Fri, 16 Mar 2018 12:15:17 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Mar 2018 05:15:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,315,1517904000"; d="scan'208";a="211922808" Received: from rosetta.fi.intel.com ([10.237.72.186]) by fmsmga006.fm.intel.com with ESMTP; 16 Mar 2018 05:15:15 -0700 Received: by rosetta.fi.intel.com (Postfix, from userid 1000) id 4F5A284008D; Fri, 16 Mar 2018 14:15:02 +0200 (EET) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Fri, 16 Mar 2018 14:14:56 +0200 Message-Id: <20180316121456.11577-8-mika.kuoppala@linux.intel.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180316121456.11577-1-mika.kuoppala@linux.intel.com> References: <20180316121456.11577-1-mika.kuoppala@linux.intel.com> Subject: [Intel-gfx] [PATCH 8/8] drm/i915/icl: Use hw engine class, instance to find irq handler X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Interrupt identity register we already read from hardware contains engine class and instance fields. Leverage these fields to find correct engine to handle the interrupt. v3: rebase on top of rps intr use correct class / instance limits (Michel) Suggested-by: Daniele Ceraolo Spurio Cc: Daniele Ceraolo Spurio Cc: Chris Wilson Cc: Tvrtko Ursulin Cc: Michel Thierry Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_irq.c | 80 +++++++++++++++-------------------------- drivers/gpu/drm/i915/i915_reg.h | 4 ++- 2 files changed, 31 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 8c4510ffe625..dd2fb2d0457f 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -413,8 +413,8 @@ static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_m } static u32 -gen11_gt_engine_intr(struct drm_i915_private * const i915, - const unsigned int bank, const unsigned int bit); +gen11_gt_engine_identity(struct drm_i915_private * const i915, + const unsigned int bank, const unsigned int bit); void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv) { @@ -428,7 +428,7 @@ void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv) */ dw = I915_READ_FW(GEN11_GT_INTR_DW0); while (dw & BIT(GEN11_GTPM)) { - gen11_gt_engine_intr(dev_priv, 0, GEN11_GTPM); + gen11_gt_engine_identity(dev_priv, 0, GEN11_GTPM); I915_WRITE_FW(GEN11_GT_INTR_DW0, BIT(GEN11_GTPM)); dw = I915_READ_FW(GEN11_GT_INTR_DW0); } @@ -2771,50 +2771,9 @@ static void __fini_wedge(struct wedge_me *w) (W)->i915; \ __fini_wedge((W))) -static void -gen11_gt_engine_irq_handler(struct drm_i915_private * const i915, - const unsigned int bank, - const unsigned int engine_n, - const u16 iir) -{ - struct intel_engine_cs ** const engine = i915->engine; - - switch (bank) { - case 0: - switch (engine_n) { - - case GEN11_RCS0: - return gen8_cs_irq_handler(engine[RCS], iir); - - case GEN11_BCS: - return gen8_cs_irq_handler(engine[BCS], iir); - - case GEN11_GTPM: - return gen6_rps_irq_handler(i915, iir); - } - case 1: - switch (engine_n) { - - case GEN11_VCS(0): - return gen8_cs_irq_handler(engine[_VCS(0)], iir); - case GEN11_VCS(1): - return gen8_cs_irq_handler(engine[_VCS(1)], iir); - case GEN11_VCS(2): - return gen8_cs_irq_handler(engine[_VCS(2)], iir); - case GEN11_VCS(3): - return gen8_cs_irq_handler(engine[_VCS(3)], iir); - - case GEN11_VECS(0): - return gen8_cs_irq_handler(engine[_VECS(0)], iir); - case GEN11_VECS(1): - return gen8_cs_irq_handler(engine[_VECS(1)], iir); - } - } -} - static u32 -gen11_gt_engine_intr(struct drm_i915_private * const i915, - const unsigned int bank, const unsigned int bit) +gen11_gt_engine_identity(struct drm_i915_private * const i915, + const unsigned int bank, const unsigned int bit) { void __iomem * const regs = i915->regs; u32 timeout_ts; @@ -2841,7 +2800,26 @@ gen11_gt_engine_intr(struct drm_i915_private * const i915, raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank), GEN11_INTR_DATA_VALID); - return ident & GEN11_INTR_ENGINE_MASK; + return ident; +} + +static void +gen11_gt_identity_handler(struct drm_i915_private * const i915, + const u32 identity) +{ + const u8 class = GEN11_INTR_ENGINE_CLASS(identity); + const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity); + const u16 iir = GEN11_INTR_ENGINE_MASK(identity); + + if (unlikely(!iir)) + return; + + if (class <= MAX_ENGINE_CLASS && instance <= MAX_ENGINE_INSTANCE) + return gen8_cs_irq_handler(i915->engine_class[class][instance], + iir); + + if (class == GEN11_GTPM) + return gen6_rps_irq_handler(i915, iir); } static void @@ -2866,12 +2844,10 @@ gen11_gt_irq_handler(struct drm_i915_private * const i915, } for_each_set_bit(bit, &intr_dw, 32) { - const u16 iir = gen11_gt_engine_intr(i915, bank, bit); - - if (unlikely(!iir)) - continue; + const u32 ident = gen11_gt_engine_identity(i915, + bank, bit); - gen11_gt_engine_irq_handler(i915, bank, bit, iir); + gen11_gt_identity_handler(i915, ident); } /* Clear must be after shared has been served for engine */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f3cc77690124..74a8f454e8a0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6826,7 +6826,9 @@ enum { #define GEN11_INTR_IDENTITY_REG0 _MMIO(0x190060) #define GEN11_INTR_IDENTITY_REG1 _MMIO(0x190064) #define GEN11_INTR_DATA_VALID (1 << 31) -#define GEN11_INTR_ENGINE_MASK (0xffff) +#define GEN11_INTR_ENGINE_MASK(x) ((x) & 0xffff) +#define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16) +#define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20) #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + (x * 4))