diff mbox

[v2,4/5] drm/i915/psr: Do not override PSR2 sink support

Message ID 20180316230501.974-4-jose.souza@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Souza, Jose March 16, 2018, 11:05 p.m. UTC 
Sink can support our PSR2 requirements but userspace can request
a resolution that PSR2 hardware do not support, in this case it
was overwritten the PSR2 sink support.
Adding another flag here, this way if requested resolution changed
to a value that PSR2 hardware can handle, PSR2 can be enabled.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c |  4 ++--
 drivers/gpu/drm/i915/i915_drv.h     |  3 ++-
 drivers/gpu/drm/i915/intel_psr.c    | 36 ++++++++++++++++++------------------
 3 files changed, 22 insertions(+), 21 deletions(-)

Comments

Rodrigo Vivi March 16, 2018, 11:26 p.m. UTC | #1 
On Fri, Mar 16, 2018 at 04:05:00PM -0700, José Roberto de Souza wrote:
> Sink can support our PSR2 requirements but userspace can request
> a resolution that PSR2 hardware do not support, in this case it
> was overwritten the PSR2 sink support.
> Adding another flag here, this way if requested resolution changed
> to a value that PSR2 hardware can handle, PSR2 can be enabled.
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c |  4 ++--
>  drivers/gpu/drm/i915/i915_drv.h     |  3 ++-
>  drivers/gpu/drm/i915/intel_psr.c    | 36 ++++++++++++++++++------------------
>  3 files changed, 22 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 5378863e3238..4366adcad56d 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2571,7 +2571,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>  		   yesno(work_busy(&dev_priv->psr.work.work)));
>  
>  	if (HAS_DDI(dev_priv)) {
> -		if (dev_priv->psr.psr2_support)
> +		if (dev_priv->psr.psr2_enabled)
>  			enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
>  		else
>  			enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
> @@ -2619,7 +2619,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>  
>  		seq_printf(m, "Performance_Counter: %u\n", psrperf);
>  	}
> -	if (dev_priv->psr.psr2_support) {
> +	if (dev_priv->psr.psr2_enabled) {
>  		u32 psr2 = I915_READ(EDP_PSR2_STATUS);
>  
>  		seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d4bc8d18f56c..d4475196f78a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -601,11 +601,12 @@ struct i915_psr {
>  	bool active;
>  	struct delayed_work work;
>  	unsigned busy_frontbuffer_bits;
> -	bool psr2_support;
> +	bool sink_psr2_support;
>  	bool link_standby;
>  	bool colorimetry_support;
>  	bool alpm;
>  	bool has_hw_tracking;
> +	bool psr2_enabled;
>  
>  	void (*enable_source)(struct intel_dp *,
>  			      const struct intel_crtc_state *);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index c5eeb13cbcfd..aa4e03f65386 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -161,15 +161,15 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>  		 */
>  		y_coord_req = intel_dp_get_y_coord_required(intel_dp);
>  
> -		dev_priv->psr.psr2_support = frame_sync_cap && y_coord_req;
> -		if (dev_priv->psr.psr2_support)
> +		dev_priv->psr.sink_psr2_support = frame_sync_cap && y_coord_req;
> +		if (dev_priv->psr.sink_psr2_support)
>  			DRM_DEBUG_KMS("PSR2 supported on sink\n");
>  		else
>  			DRM_DEBUG_KMS("PSR2 not supported on sink"
>  				      "(frame sync: %d Y-coord required: %d)\n",
>  				      frame_sync_cap, y_coord_req);
>  
> -		if (dev_priv->psr.psr2_support) {
> +		if (dev_priv->psr.sink_psr2_support) {
>  			dev_priv->psr.colorimetry_support =
>  				intel_dp_get_colorimetry_status(intel_dp);
>  			dev_priv->psr.alpm =
> @@ -210,7 +210,7 @@ static void hsw_psr_setup_vsc(struct intel_dp *intel_dp,
>  	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
>  	struct edp_vsc_psr psr_vsc;
>  
> -	if (dev_priv->psr.psr2_support) {
> +	if (dev_priv->psr.psr2_enabled) {
>  		/* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
>  		memset(&psr_vsc, 0, sizeof(psr_vsc));
>  		psr_vsc.sdp_header.HB0 = 0;
> @@ -282,12 +282,12 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>  	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
>  
>  	/* Enable AUX frame sync at sink */
> -	if (dev_priv->psr.psr2_support)
> +	if (dev_priv->psr.psr2_enabled)
>  		drm_dp_dpcd_writeb(&intel_dp->aux,
>  				DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
>  				DP_AUX_FRAME_SYNC_ENABLE);
>  	/* Enable ALPM at sink for psr2 */
> -	if (dev_priv->psr.psr2_support && dev_priv->psr.alpm)
> +	if (dev_priv->psr.psr2_enabled && dev_priv->psr.alpm)
>  		drm_dp_dpcd_writeb(&intel_dp->aux,
>  				DP_RECEIVER_ALPM_CONFIG,
>  				DP_ALPM_ENABLE);
> @@ -455,7 +455,7 @@ static void hsw_psr_activate(struct intel_dp *intel_dp)
>  	 */
>  
>  	/* psr1 and psr2 are mutually exclusive.*/
> -	if (dev_priv->psr.psr2_support)
> +	if (dev_priv->psr.psr2_enabled)
>  		hsw_activate_psr2(intel_dp);
>  	else
>  		hsw_activate_psr1(intel_dp);
> @@ -475,7 +475,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  	 * dynamically during PSR enable, and extracted from sink
>  	 * caps during eDP detection.
>  	 */
> -	if (!dev_priv->psr.psr2_support)
> +	if (!dev_priv->psr.sink_psr2_support)
>  		return false;
>  
>  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> @@ -574,7 +574,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
>  	struct drm_device *dev = intel_dig_port->base.base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
> -	if (dev_priv->psr.psr2_support)
> +	if (dev_priv->psr.psr2_enabled)
>  		WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
>  	else
>  		WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
> @@ -595,7 +595,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
>  
>  	psr_aux_io_power_get(intel_dp);
>  
> -	if (dev_priv->psr.psr2_support) {
> +	if (dev_priv->psr.psr2_enabled) {
>  		u32 chicken = PSR2_VSC_ENABLE_PROG_HEADER
>  			      | PSR2_ADD_VERTICAL_LINE_COUNT;
>  		I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
> @@ -648,7 +648,7 @@ void intel_psr_enable(struct intel_dp *intel_dp,
>  		goto unlock;
>  	}
>  
> -	dev_priv->psr.psr2_support = crtc_state->has_psr2;
> +	dev_priv->psr.psr2_enabled = crtc_state->has_psr2;
>  	dev_priv->psr.busy_frontbuffer_bits = 0;
>  
>  	dev_priv->psr.setup_vsc(intel_dp, crtc_state);
> @@ -718,12 +718,12 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
>  		i915_reg_t psr_status;
>  		u32 psr_status_mask;
>  
> -		if (dev_priv->psr.psr2_support)
> +		if (dev_priv->psr.psr2_enabled)
>  			drm_dp_dpcd_writeb(&intel_dp->aux,
>  					DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
>  					0);
>  
> -		if (dev_priv->psr.psr2_support) {
> +		if (dev_priv->psr.psr2_enabled) {
>  			psr_status = EDP_PSR2_STATUS;
>  			psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
>  
> @@ -747,7 +747,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
>  
>  		dev_priv->psr.active = false;
>  	} else {
> -		if (dev_priv->psr.psr2_support)
> +		if (dev_priv->psr.psr2_enabled)
>  			WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
>  		else
>  			WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
> @@ -807,7 +807,7 @@ static void intel_psr_work(struct work_struct *work)
>  	 * and be ready for re-enable.
>  	 */
>  	if (HAS_DDI(dev_priv)) {
> -		if (dev_priv->psr.psr2_support) {
> +		if (dev_priv->psr.psr2_enabled) {
>  			if (intel_wait_for_register(dev_priv,
>  						    EDP_PSR2_STATUS,
>  						    EDP_PSR2_STATUS_STATE_MASK,
> @@ -866,11 +866,11 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
>  		return;
>  
>  	if (HAS_DDI(dev_priv)) {
> -		if (dev_priv->psr.psr2_support)
> +		if (dev_priv->psr.psr2_enabled)
>  			drm_dp_dpcd_writeb(&intel_dp->aux,
>  					DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
>  					0);
> -		if (dev_priv->psr.psr2_support) {
> +		if (dev_priv->psr.psr2_enabled) {
>  			val = I915_READ(EDP_PSR2_CTL);
>  			WARN_ON(!(val & EDP_PSR2_ENABLE));
>  			I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
> @@ -1039,7 +1039,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
>  
>  	/* By definition flush = invalidate + flush */
>  	if (frontbuffer_bits) {
> -		if (dev_priv->psr.psr2_support ||
> +		if (dev_priv->psr.psr2_enabled ||
>  		    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  			intel_psr_exit(dev_priv);
>  		} else {
> -- 
> 2.16.2
>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 5378863e3238..4366adcad56d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2571,7 +2571,7 @@  static int i915_edp_psr_status(struct seq_file *m, void *data)
 		   yesno(work_busy(&dev_priv->psr.work.work)));
 
 	if (HAS_DDI(dev_priv)) {
-		if (dev_priv->psr.psr2_support)
+		if (dev_priv->psr.psr2_enabled)
 			enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
 		else
 			enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
@@ -2619,7 +2619,7 @@  static int i915_edp_psr_status(struct seq_file *m, void *data)
 
 		seq_printf(m, "Performance_Counter: %u\n", psrperf);
 	}
-	if (dev_priv->psr.psr2_support) {
+	if (dev_priv->psr.psr2_enabled) {
 		u32 psr2 = I915_READ(EDP_PSR2_STATUS);
 
 		seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d4bc8d18f56c..d4475196f78a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -601,11 +601,12 @@  struct i915_psr {
 	bool active;
 	struct delayed_work work;
 	unsigned busy_frontbuffer_bits;
-	bool psr2_support;
+	bool sink_psr2_support;
 	bool link_standby;
 	bool colorimetry_support;
 	bool alpm;
 	bool has_hw_tracking;
+	bool psr2_enabled;
 
 	void (*enable_source)(struct intel_dp *,
 			      const struct intel_crtc_state *);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index c5eeb13cbcfd..aa4e03f65386 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -161,15 +161,15 @@  void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 		 */
 		y_coord_req = intel_dp_get_y_coord_required(intel_dp);
 
-		dev_priv->psr.psr2_support = frame_sync_cap && y_coord_req;
-		if (dev_priv->psr.psr2_support)
+		dev_priv->psr.sink_psr2_support = frame_sync_cap && y_coord_req;
+		if (dev_priv->psr.sink_psr2_support)
 			DRM_DEBUG_KMS("PSR2 supported on sink\n");
 		else
 			DRM_DEBUG_KMS("PSR2 not supported on sink"
 				      "(frame sync: %d Y-coord required: %d)\n",
 				      frame_sync_cap, y_coord_req);
 
-		if (dev_priv->psr.psr2_support) {
+		if (dev_priv->psr.sink_psr2_support) {
 			dev_priv->psr.colorimetry_support =
 				intel_dp_get_colorimetry_status(intel_dp);
 			dev_priv->psr.alpm =
@@ -210,7 +210,7 @@  static void hsw_psr_setup_vsc(struct intel_dp *intel_dp,
 	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 	struct edp_vsc_psr psr_vsc;
 
-	if (dev_priv->psr.psr2_support) {
+	if (dev_priv->psr.psr2_enabled) {
 		/* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
 		memset(&psr_vsc, 0, sizeof(psr_vsc));
 		psr_vsc.sdp_header.HB0 = 0;
@@ -282,12 +282,12 @@  static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
 
 	/* Enable AUX frame sync at sink */
-	if (dev_priv->psr.psr2_support)
+	if (dev_priv->psr.psr2_enabled)
 		drm_dp_dpcd_writeb(&intel_dp->aux,
 				DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
 				DP_AUX_FRAME_SYNC_ENABLE);
 	/* Enable ALPM at sink for psr2 */
-	if (dev_priv->psr.psr2_support && dev_priv->psr.alpm)
+	if (dev_priv->psr.psr2_enabled && dev_priv->psr.alpm)
 		drm_dp_dpcd_writeb(&intel_dp->aux,
 				DP_RECEIVER_ALPM_CONFIG,
 				DP_ALPM_ENABLE);
@@ -455,7 +455,7 @@  static void hsw_psr_activate(struct intel_dp *intel_dp)
 	 */
 
 	/* psr1 and psr2 are mutually exclusive.*/
-	if (dev_priv->psr.psr2_support)
+	if (dev_priv->psr.psr2_enabled)
 		hsw_activate_psr2(intel_dp);
 	else
 		hsw_activate_psr1(intel_dp);
@@ -475,7 +475,7 @@  static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 	 * dynamically during PSR enable, and extracted from sink
 	 * caps during eDP detection.
 	 */
-	if (!dev_priv->psr.psr2_support)
+	if (!dev_priv->psr.sink_psr2_support)
 		return false;
 
 	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
@@ -574,7 +574,7 @@  static void intel_psr_activate(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
-	if (dev_priv->psr.psr2_support)
+	if (dev_priv->psr.psr2_enabled)
 		WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
 	else
 		WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
@@ -595,7 +595,7 @@  static void hsw_psr_enable_source(struct intel_dp *intel_dp,
 
 	psr_aux_io_power_get(intel_dp);
 
-	if (dev_priv->psr.psr2_support) {
+	if (dev_priv->psr.psr2_enabled) {
 		u32 chicken = PSR2_VSC_ENABLE_PROG_HEADER
 			      | PSR2_ADD_VERTICAL_LINE_COUNT;
 		I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
@@ -648,7 +648,7 @@  void intel_psr_enable(struct intel_dp *intel_dp,
 		goto unlock;
 	}
 
-	dev_priv->psr.psr2_support = crtc_state->has_psr2;
+	dev_priv->psr.psr2_enabled = crtc_state->has_psr2;
 	dev_priv->psr.busy_frontbuffer_bits = 0;
 
 	dev_priv->psr.setup_vsc(intel_dp, crtc_state);
@@ -718,12 +718,12 @@  static void hsw_psr_disable(struct intel_dp *intel_dp,
 		i915_reg_t psr_status;
 		u32 psr_status_mask;
 
-		if (dev_priv->psr.psr2_support)
+		if (dev_priv->psr.psr2_enabled)
 			drm_dp_dpcd_writeb(&intel_dp->aux,
 					DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
 					0);
 
-		if (dev_priv->psr.psr2_support) {
+		if (dev_priv->psr.psr2_enabled) {
 			psr_status = EDP_PSR2_STATUS;
 			psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
 
@@ -747,7 +747,7 @@  static void hsw_psr_disable(struct intel_dp *intel_dp,
 
 		dev_priv->psr.active = false;
 	} else {
-		if (dev_priv->psr.psr2_support)
+		if (dev_priv->psr.psr2_enabled)
 			WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
 		else
 			WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
@@ -807,7 +807,7 @@  static void intel_psr_work(struct work_struct *work)
 	 * and be ready for re-enable.
 	 */
 	if (HAS_DDI(dev_priv)) {
-		if (dev_priv->psr.psr2_support) {
+		if (dev_priv->psr.psr2_enabled) {
 			if (intel_wait_for_register(dev_priv,
 						    EDP_PSR2_STATUS,
 						    EDP_PSR2_STATUS_STATE_MASK,
@@ -866,11 +866,11 @@  static void intel_psr_exit(struct drm_i915_private *dev_priv)
 		return;
 
 	if (HAS_DDI(dev_priv)) {
-		if (dev_priv->psr.psr2_support)
+		if (dev_priv->psr.psr2_enabled)
 			drm_dp_dpcd_writeb(&intel_dp->aux,
 					DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
 					0);
-		if (dev_priv->psr.psr2_support) {
+		if (dev_priv->psr.psr2_enabled) {
 			val = I915_READ(EDP_PSR2_CTL);
 			WARN_ON(!(val & EDP_PSR2_ENABLE));
 			I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
@@ -1039,7 +1039,7 @@  void intel_psr_flush(struct drm_i915_private *dev_priv,
 
 	/* By definition flush = invalidate + flush */
 	if (frontbuffer_bits) {
-		if (dev_priv->psr.psr2_support ||
+		if (dev_priv->psr.psr2_enabled ||
 		    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 			intel_psr_exit(dev_priv);
 		} else {