From patchwork Mon Mar 19 18:16:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10293867 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AC866602C2 for ; Mon, 19 Mar 2018 18:16:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9C75228543 for ; Mon, 19 Mar 2018 18:16:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9137828AB1; Mon, 19 Mar 2018 18:16:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 23AC629314 for ; Mon, 19 Mar 2018 18:16:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 497726E5F0; Mon, 19 Mar 2018 18:16:40 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3EC896E5EC for ; Mon, 19 Mar 2018 18:16:37 +0000 (UTC) Received: by mail-wm0-x242.google.com with SMTP id f19so4337453wmc.0 for ; Mon, 19 Mar 2018 11:16:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ursulin-net.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kvrJnxXckINI2XQbbl0Yi5lcNU/XkSappjHQ+J5W9Q8=; b=wo6T+nLzEjDYc/3TJkNe8jo9W39MIP2rg8syr4rGb+2KnVDz33hNeRD1FuFIVEqRAt u/FsmCr3AUE0LVL5Zg+J0p+bBpN7P9WBIeFNl2Liq/gaNabWX8HDz2nEpjC4UgGeFo28 +ZbJL4fQqeL3NdLMTH5FOovJVgXz/iC+x4cAOY0uu1gjOHwPV6N0aoVrOwJA2kBsnAyY L8L+WH/hp3lsJd46u4oTvltYKpK/WVh74k7/j4q+G3FRW+finsvG5QJE9IIZZgYR9e0l wbWS8RMdDyW4fTiGYju7lt8JhVu4RvBHnB7jTqVN2kpmwDiTlluUz2aS3D7FtavDB55j hAmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kvrJnxXckINI2XQbbl0Yi5lcNU/XkSappjHQ+J5W9Q8=; b=J0KyEywgsB1vFQiS1MdhbnF9kD+XE4IzW/sFvrtmUfN2uz/FtVcT886tmoGVK1Rm/T qbwKjY9UuHZpUOsnQXq0ZKFohRg9l9qKHl/3KdTzrYSluAIwJ4XW3MSwiEcsWoiD7It+ BqD0/TaAhEGPNw+IvRJEPg6rjK60TbVDLHWEIfR3dTPZov54hBwWTQ2GQv8cKKQoNWoK 4NuKJpnzNLrwIGTH78pI0lLEHPltamWoggxb/Xu6K6w0NlyUfBwcSsWisICsqANvV7xW iVnSBZqH4ohED36vJoyGV8VF3w3yJ78HL/s9z3EuuWfRN/cTwLKtxsPONGxFrFz+uL4U 8T7Q== X-Gm-Message-State: AElRT7Galqiaa6DA7f7uaPmy01gXhMPbwDJrlX492/0LpyH+7d/93Spj TPYiW6ZDGOza9YLRyx+53GJeczSy X-Google-Smtp-Source: AG47ELtbFPQ0k0fkXL6kn6Nq+9QJpL+utUkRoBPFzaMcSwp6g18rbzxKDcrgnqoTnukScRLffRtL2g== X-Received: by 10.28.39.1 with SMTP id n1mr8965746wmn.150.1521483395730; Mon, 19 Mar 2018 11:16:35 -0700 (PDT) Received: from localhost.localdomain ([95.146.144.186]) by smtp.gmail.com with ESMTPSA id r19sm1234030wmd.48.2018.03.19.11.16.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 19 Mar 2018 11:16:35 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Mon, 19 Mar 2018 18:16:19 +0000 Message-Id: <20180319181625.29292-2-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180319181625.29292-1-tvrtko.ursulin@linux.intel.com> References: <20180319181625.29292-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [PATCH 1/7] drm/i915/pmu: Fix enable count array size and bounds checking X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin Enable count array is supposed to have one counter for each possible engine sampler. As such array sizing and bounds checking is not correct when more engine samplers are added. At the same time tidy the assert for readability and robustness. Signed-off-by: Tvrtko Ursulin Fixes: b46a33e271ed ("drm/i915/pmu: Expose a PMU interface for perf queries") Cc: Chris Wilson --- drivers/gpu/drm/i915/i915_pmu.c | 13 +++++++++---- drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 11fb76bd3860..eb60943671b3 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -549,7 +549,8 @@ static void i915_pmu_enable(struct perf_event *event) * Update the bitmask of enabled events and increment * the event reference counter. */ - GEM_BUG_ON(bit >= I915_PMU_MASK_BITS); + BUILD_BUG_ON(ARRAY_SIZE(i915->pmu.enable_count) != I915_PMU_MASK_BITS); + GEM_BUG_ON(bit >= ARRAY_SIZE(i915->pmu.enable_count)); GEM_BUG_ON(i915->pmu.enable_count[bit] == ~0); i915->pmu.enable |= BIT_ULL(bit); i915->pmu.enable_count[bit]++; @@ -573,7 +574,10 @@ static void i915_pmu_enable(struct perf_event *event) GEM_BUG_ON(!engine); engine->pmu.enable |= BIT(sample); - GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS); + BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.enable_count) != + (1 << I915_PMU_SAMPLE_BITS)); + GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count)); + GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample)); GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0); engine->pmu.enable_count[sample]++; } @@ -605,7 +609,8 @@ static void i915_pmu_disable(struct perf_event *event) engine_event_class(event), engine_event_instance(event)); GEM_BUG_ON(!engine); - GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS); + GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count)); + GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample)); GEM_BUG_ON(engine->pmu.enable_count[sample] == 0); /* * Decrement the reference count and clear the enabled @@ -615,7 +620,7 @@ static void i915_pmu_disable(struct perf_event *event) engine->pmu.enable &= ~BIT(sample); } - GEM_BUG_ON(bit >= I915_PMU_MASK_BITS); + GEM_BUG_ON(bit >= ARRAY_SIZE(i915->pmu.enable_count)); GEM_BUG_ON(i915->pmu.enable_count[bit] == 0); /* * Decrement the reference count and clear the enabled diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 1f50727a5ddb..828a1f924405 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -391,7 +391,7 @@ struct intel_engine_cs { * * Index number corresponds to the bit number from @enable. */ - unsigned int enable_count[I915_PMU_SAMPLE_BITS]; + unsigned int enable_count[1 << I915_PMU_SAMPLE_BITS]; /** * @sample: Counter values for sampling events. *