From patchwork Mon Mar 19 18:16:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10293875 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 382C660386 for ; Mon, 19 Mar 2018 18:16:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2193328AB1 for ; Mon, 19 Mar 2018 18:16:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1632F29314; Mon, 19 Mar 2018 18:16:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 708C928AB1 for ; Mon, 19 Mar 2018 18:16:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4E1546E5F6; Mon, 19 Mar 2018 18:16:49 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) by gabe.freedesktop.org (Postfix) with ESMTPS id E20A56E5EF for ; Mon, 19 Mar 2018 18:16:39 +0000 (UTC) Received: by mail-wm0-x243.google.com with SMTP id l9so7815368wmh.2 for ; Mon, 19 Mar 2018 11:16:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ursulin-net.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8DMexXRuGnicrP6949gP8SuvOcYqCVZ4VHRBKrmEAsQ=; b=RmT4TtU5ZHfLea956LpinX4yvw16pq/t6/0OYb/MCAmqyTwiCLueTjmvphRPk7a23D NRhhXj9VZgloWoJZ34vfyiDg8OrZQQBUN2CjEfccUuyD+6v9SYn/93nej3/VnvC4cTHI Ih7YOQYrlB1P6ln4rQ/ykxHmUZ/9u7Ogu/taJiHOYCc0RR5QFfYrK3AgyTZzq1rGfqse HCYLE5iNNuR7/wJ9abGW9rQtta+Zy7lIVeluvHrH4vkQxi1CLj8Lidt08JI/XoqNcBk6 F9FY2wxJSf7GUprgGAsjHGEZVxTf43Y0L+vF7NfgJnN5+DInmOnnO3TVjcnsJqqgVIwn 4hTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8DMexXRuGnicrP6949gP8SuvOcYqCVZ4VHRBKrmEAsQ=; b=TYjj0KqCxHNj6ZWwjqAIzASFicH7/4/vRWv3wR1gTth57ok5hT10nUBkNCGvBOrg4B pN32RpLnCd0ylCHi+4XhPygm7VPPU7EpEwHj6Wog7BD9SX+E2Ksz31LD07wZgHTl0IYQ GbmTK4Hjr44HErKvhtU6OXkUhLsaisama0CNUwhSvTOAL9ZIh0pB2H5wpeTKm8MWDuYZ kiHmXj2wGjWIjHVzsMSn5jC4vepuRrnUqWwjLTv5bbZP6gBtY8depXa76AIFblQiCSzK 6Qp1AyLzJqx3Ip6S1afj/+2PZ0AEnIBLLr+DCdBUgR/LsEZtzIZ0vnUXqG5X4Q2SRQh4 /+rQ== X-Gm-Message-State: AElRT7EzvcopAMh9weiVDwAEKFSX16E8HBzsO+6mYfwv9WqnlRc0AcSE Ma+sSPGbosmjkCBSPC7J8QIQFMBX X-Google-Smtp-Source: AG47ELta+dfBnOqdLsR9zUl32yqIZ2xstnUSbTYRtoEFsb9lef9ygm9LPu1yI0ecOildR3dHMSCZ5A== X-Received: by 10.28.174.80 with SMTP id x77mr9892771wme.130.1521483398340; Mon, 19 Mar 2018 11:16:38 -0700 (PDT) Received: from localhost.localdomain ([95.146.144.186]) by smtp.gmail.com with ESMTPSA id r19sm1234030wmd.48.2018.03.19.11.16.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 19 Mar 2018 11:16:37 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Mon, 19 Mar 2018 18:16:22 +0000 Message-Id: <20180319181625.29292-5-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180319181625.29292-1-tvrtko.ursulin@linux.intel.com> References: <20180319181625.29292-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [PATCH 4/7] drm/i915/pmu: Add queued counter X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin We add a PMU counter to expose the number of requests which have been submitted from userspace but are not yet runnable due dependencies and unsignaled fences. This is useful to analyze the overall load of the system. v2: * Rebase for name change and re-order. * Drop floating point constant. (Chris Wilson) v3: * Change scale to 1024 for faster arithmetics. (Chris Wilson) Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_pmu.c | 40 +++++++++++++++++++++++++++++---- drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +- include/uapi/drm/i915_drm.h | 9 +++++++- 3 files changed, 45 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index eb60943671b3..07f5cac97b56 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -15,7 +15,8 @@ #define ENGINE_SAMPLE_MASK \ (BIT(I915_SAMPLE_BUSY) | \ BIT(I915_SAMPLE_WAIT) | \ - BIT(I915_SAMPLE_SEMA)) + BIT(I915_SAMPLE_SEMA) | \ + BIT(I915_SAMPLE_QUEUED)) #define ENGINE_SAMPLE_BITS (1 << I915_PMU_SAMPLE_BITS) @@ -199,6 +200,11 @@ static void engines_sample(struct drm_i915_private *dev_priv) update_sample(&engine->pmu.sample[I915_SAMPLE_SEMA], PERIOD, !!(val & RING_WAIT_SEMAPHORE)); + + if (engine->pmu.enable & BIT(I915_SAMPLE_QUEUED)) + update_sample(&engine->pmu.sample[I915_SAMPLE_QUEUED], + I915_SAMPLE_QUEUED_DIVISOR, + atomic_read(&engine->request_stats.queued)); } if (fw) @@ -296,6 +302,7 @@ engine_event_status(struct intel_engine_cs *engine, switch (sample) { case I915_SAMPLE_BUSY: case I915_SAMPLE_WAIT: + case I915_SAMPLE_QUEUED: break; case I915_SAMPLE_SEMA: if (INTEL_GEN(engine->i915) < 6) @@ -497,6 +504,9 @@ static u64 __i915_pmu_event_read(struct perf_event *event) } else { val = engine->pmu.sample[sample].cur; } + + if (sample == I915_SAMPLE_QUEUED) + val = div_u64(val, FREQUENCY); } else { switch (event->attr.config) { case I915_PMU_ACTUAL_FREQUENCY: @@ -752,6 +762,16 @@ static const struct attribute_group *i915_pmu_attr_groups[] = { { \ .sample = (__sample), \ .name = (__name), \ + .suffix = "unit", \ + .value = "ns", \ +} + +#define __engine_event_scale(__sample, __name, __scale) \ +{ \ + .sample = (__sample), \ + .name = (__name), \ + .suffix = "scale", \ + .value = (__scale), \ } static struct i915_ext_attribute * @@ -779,6 +799,9 @@ add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name, return ++attr; } +/* No brackets or quotes below please. */ +#define I915_SAMPLE_QUEUED_SCALE 0.0009765625 + static struct attribute ** create_event_attributes(struct drm_i915_private *i915) { @@ -795,10 +818,14 @@ create_event_attributes(struct drm_i915_private *i915) static const struct { enum drm_i915_pmu_engine_sample sample; char *name; + char *suffix; + char *value; } engine_events[] = { __engine_event(I915_SAMPLE_BUSY, "busy"), __engine_event(I915_SAMPLE_SEMA, "sema"), __engine_event(I915_SAMPLE_WAIT, "wait"), + __engine_event_scale(I915_SAMPLE_QUEUED, "queued", + __stringify(I915_SAMPLE_QUEUED_SCALE)), }; unsigned int count = 0; struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter; @@ -808,6 +835,9 @@ create_event_attributes(struct drm_i915_private *i915) enum intel_engine_id id; unsigned int i; + BUILD_BUG_ON(I915_SAMPLE_QUEUED_DIVISOR != + (1 / I915_SAMPLE_QUEUED_SCALE)); + /* Count how many counters we will be exposing. */ for (i = 0; i < ARRAY_SIZE(events); i++) { if (!config_status(i915, events[i].config)) @@ -885,13 +915,15 @@ create_event_attributes(struct drm_i915_private *i915) engine->instance, engine_events[i].sample)); - str = kasprintf(GFP_KERNEL, "%s-%s.unit", - engine->name, engine_events[i].name); + str = kasprintf(GFP_KERNEL, "%s-%s.%s", + engine->name, engine_events[i].name, + engine_events[i].suffix); if (!str) goto err; *attr_iter++ = &pmu_iter->attr.attr; - pmu_iter = add_pmu_attr(pmu_iter, str, "ns"); + pmu_iter = add_pmu_attr(pmu_iter, str, + engine_events[i].value); } } diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 810ef79959f2..62a198f5ba80 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -414,7 +414,7 @@ struct intel_engine_cs { * * Our internal timer stores the current counters in this field. */ -#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_SEMA + 1) +#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_QUEUED + 1) struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_MAX]; } pmu; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 7f5634ce8e88..6094cc9ca6d9 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -110,9 +110,13 @@ enum drm_i915_gem_engine_class { enum drm_i915_pmu_engine_sample { I915_SAMPLE_BUSY = 0, I915_SAMPLE_WAIT = 1, - I915_SAMPLE_SEMA = 2 + I915_SAMPLE_SEMA = 2, + I915_SAMPLE_QUEUED = 3 }; + /* Divide counter value by divisor to get the real value. */ +#define I915_SAMPLE_QUEUED_DIVISOR (1024) + #define I915_PMU_SAMPLE_BITS (4) #define I915_PMU_SAMPLE_MASK (0xf) #define I915_PMU_SAMPLE_INSTANCE_BITS (8) @@ -133,6 +137,9 @@ enum drm_i915_pmu_engine_sample { #define I915_PMU_ENGINE_SEMA(class, instance) \ __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) +#define I915_PMU_ENGINE_QUEUED(class, instance) \ + __I915_PMU_ENGINE(class, instance, I915_SAMPLE_QUEUED) + #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)