From patchwork Mon Mar 19 18:16:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10293873 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 87412602C2 for ; Mon, 19 Mar 2018 18:16:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7455728543 for ; Mon, 19 Mar 2018 18:16:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6930029314; Mon, 19 Mar 2018 18:16:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 056D028543 for ; Mon, 19 Mar 2018 18:16:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5B8F56E30B; Mon, 19 Mar 2018 18:16:45 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id 66CA06E5EF for ; Mon, 19 Mar 2018 18:16:41 +0000 (UTC) Received: by mail-wm0-x244.google.com with SMTP id t6so17618335wmt.5 for ; Mon, 19 Mar 2018 11:16:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ursulin-net.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=PKSw7nY5gPmvtjD/R4hrbM9KMDCJ+9nTp76TW2Rso8A=; b=vQJ77tHWuH/UgAc7yP5IQugqEDqdNWIFVK1bM4Vadz3xLyNSYQwlVJqb2l+xcEkMzA WxuiGpRBAwf2toW2DF5Xro5url5aS3/rUHbQ5aEe+bf7PKFU6ESqT6B3aUW02Nntbx2W 26pDWXk783GJmAmA7IZtC9EWOQgRXshtTkcfo/I1fOnhrcBaUwxc0dJ5/tiJ1xM/qCCj ypx/Z5Pg207x0HRUFEyfBvKiqvxaP24jHgXxU/cEvm2MGhSGGAG7g/BVhCJArQ81OTxS nWjdxyc2DyJwOV+QMzNQ9Q4y6DH9Hqt8tnvNwyE8pTny1OUUrdireP3wavoE5EHaa8Kn mRIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=PKSw7nY5gPmvtjD/R4hrbM9KMDCJ+9nTp76TW2Rso8A=; b=lnHtXs5lLVjWg0uGhrphaNxNK8pLp7PCDfSdXnBmT/R6C4Shhgb3OTreUk7OpdVo0n M+Q1jfUXuZHpZUE8wGkSndXi1kkHb/OZ1h6v/VHWGg3qDvTu2TtPpsjx/6jinwgGtU3W OnL5wmHs8f2aQn6QlwHz6X8sBvPvaTdTq9HsTqAYTdye+KcgNog1QSgKRcwh8vSgX30L LkXdhzRn+gPueNYxmWzXDIxy00d+VVvCJN8MtJObpPRt27necgw62+Hgqo5Cg/CEKtkl vMyLJhMn5+VBe0QE9JwJT1EOs8zO7t2zcIP7No0ty9njlmrQvQTreV6oYJSTZ40cbD6h TWWQ== X-Gm-Message-State: AElRT7EYnJ2g6sRXTl2tUeTNLoO2aVctxgVKW5PMsfpRB/MIBCm/7Cxt E9aXEurthPusNqIq68KaPvRwCX+r X-Google-Smtp-Source: AG47ELtJw/qB03Vnq4HyvTOJaUNtYbbdb9h8WtJKP8DWGG36Kosf3rtexbzUL5+jcN2mqEphgQk5Hg== X-Received: by 10.28.136.18 with SMTP id k18mr10060759wmd.111.1521483399812; Mon, 19 Mar 2018 11:16:39 -0700 (PDT) Received: from localhost.localdomain ([95.146.144.186]) by smtp.gmail.com with ESMTPSA id r19sm1234030wmd.48.2018.03.19.11.16.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 19 Mar 2018 11:16:39 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Mon, 19 Mar 2018 18:16:24 +0000 Message-Id: <20180319181625.29292-7-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180319181625.29292-1-tvrtko.ursulin@linux.intel.com> References: <20180319181625.29292-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [PATCH 6/7] drm/i915/pmu: Add running counter X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin We add a PMU counter to expose the number of requests currently executing on the GPU. This is useful to analyze the overall load of the system. v2: * Rebase. * Drop floating point constant. (Chris Wilson) v3: * Change scale to 1024 for faster arithmetics. (Chris Wilson) Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_pmu.c | 18 ++++++++++++++++-- drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +- include/uapi/drm/i915_drm.h | 5 +++++ 3 files changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index afc561e1aa92..bd7e695fc663 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -17,7 +17,8 @@ BIT(I915_SAMPLE_WAIT) | \ BIT(I915_SAMPLE_SEMA) | \ BIT(I915_SAMPLE_QUEUED) | \ - BIT(I915_SAMPLE_RUNNABLE)) + BIT(I915_SAMPLE_RUNNABLE) | \ + BIT(I915_SAMPLE_RUNNING)) #define ENGINE_SAMPLE_BITS (1 << I915_PMU_SAMPLE_BITS) @@ -211,6 +212,11 @@ static void engines_sample(struct drm_i915_private *dev_priv) update_sample(&engine->pmu.sample[I915_SAMPLE_RUNNABLE], I915_SAMPLE_RUNNABLE_DIVISOR, engine->request_stats.runnable); + + if (engine->pmu.enable & BIT(I915_SAMPLE_RUNNING)) + update_sample(&engine->pmu.sample[I915_SAMPLE_RUNNING], + I915_SAMPLE_RUNNING_DIVISOR, + last_seqno - current_seqno); } if (fw) @@ -310,6 +316,7 @@ engine_event_status(struct intel_engine_cs *engine, case I915_SAMPLE_WAIT: case I915_SAMPLE_QUEUED: case I915_SAMPLE_RUNNABLE: + case I915_SAMPLE_RUNNING: break; case I915_SAMPLE_SEMA: if (INTEL_GEN(engine->i915) < 6) @@ -513,7 +520,8 @@ static u64 __i915_pmu_event_read(struct perf_event *event) } if (sample == I915_SAMPLE_QUEUED || - sample == I915_SAMPLE_RUNNABLE) + sample == I915_SAMPLE_RUNNABLE || + sample == I915_SAMPLE_RUNNING) val = div_u64(val, FREQUENCY); } else { switch (event->attr.config) { @@ -810,6 +818,7 @@ add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name, /* No brackets or quotes below please. */ #define I915_SAMPLE_QUEUED_SCALE 0.0009765625 #define I915_SAMPLE_RUNNABLE_SCALE 0.0009765625 +#define I915_SAMPLE_RUNNING_SCALE 0.0009765625 static struct attribute ** create_event_attributes(struct drm_i915_private *i915) @@ -837,6 +846,8 @@ create_event_attributes(struct drm_i915_private *i915) __stringify(I915_SAMPLE_QUEUED_SCALE)), __engine_event_scale(I915_SAMPLE_RUNNABLE, "runnable", __stringify(I915_SAMPLE_RUNNABLE_SCALE)), + __engine_event_scale(I915_SAMPLE_RUNNING, "running", + __stringify(I915_SAMPLE_RUNNING_SCALE)), }; unsigned int count = 0; struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter; @@ -852,6 +863,9 @@ create_event_attributes(struct drm_i915_private *i915) BUILD_BUG_ON(I915_SAMPLE_RUNNABLE_DIVISOR != (1 / I915_SAMPLE_RUNNABLE_SCALE)); + BUILD_BUG_ON(I915_SAMPLE_RUNNING_DIVISOR != + (1 / I915_SAMPLE_RUNNING_SCALE)); + /* Count how many counters we will be exposing. */ for (i = 0; i < ARRAY_SIZE(events); i++) { if (!config_status(i915, events[i].config)) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 5d7532b185fe..fe1b7d0a94e9 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -414,7 +414,7 @@ struct intel_engine_cs { * * Our internal timer stores the current counters in this field. */ -#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_RUNNABLE + 1) +#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_RUNNING + 1) struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_MAX]; } pmu; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index cf0265b20e37..9a00c30e4071 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -113,11 +113,13 @@ enum drm_i915_pmu_engine_sample { I915_SAMPLE_SEMA = 2, I915_SAMPLE_QUEUED = 3, I915_SAMPLE_RUNNABLE = 4, + I915_SAMPLE_RUNNING = 5, }; /* Divide counter value by divisor to get the real value. */ #define I915_SAMPLE_QUEUED_DIVISOR (1024) #define I915_SAMPLE_RUNNABLE_DIVISOR (1024) +#define I915_SAMPLE_RUNNING_DIVISOR (1024) #define I915_PMU_SAMPLE_BITS (4) #define I915_PMU_SAMPLE_MASK (0xf) @@ -145,6 +147,9 @@ enum drm_i915_pmu_engine_sample { #define I915_PMU_ENGINE_RUNNABLE(class, instance) \ __I915_PMU_ENGINE(class, instance, I915_SAMPLE_RUNNABLE) +#define I915_PMU_ENGINE_RUNNING(class, instance) \ + __I915_PMU_ENGINE(class, instance, I915_SAMPLE_RUNNING) + #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)