From patchwork Tue Mar 20 22:41:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dhinakaran Pandiyan X-Patchwork-Id: 10298129 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 067E460386 for ; Tue, 20 Mar 2018 22:42:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E735128179 for ; Tue, 20 Mar 2018 22:42:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DBEEA28329; Tue, 20 Mar 2018 22:42:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 462D028179 for ; Tue, 20 Mar 2018 22:42:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 13DC16E824; Tue, 20 Mar 2018 22:42:34 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id ED3EF6E008 for ; Tue, 20 Mar 2018 22:42:26 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Mar 2018 15:42:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,337,1517904000"; d="scan'208";a="26639941" Received: from dk-thinkpad-x260.jf.intel.com ([10.54.75.46]) by orsmga007.jf.intel.com with ESMTP; 20 Mar 2018 15:42:25 -0700 From: Dhinakaran Pandiyan To: intel-gfx@lists.freedesktop.org Date: Tue, 20 Mar 2018 15:41:49 -0700 Message-Id: <20180320224151.6009-4-dhinakaran.pandiyan@intel.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180320224151.6009-1-dhinakaran.pandiyan@intel.com> References: <20180320224151.6009-1-dhinakaran.pandiyan@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/5] drm/i915: Enable edp psr error interrupts on bdw+ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Vetter , Dhinakaran Pandiyan , Rodrigo Vivi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Daniel Vetter Plug in the bdw+ irq handling for PSR interrupts. bdw+ supports psr on any transcoder in theory, though the we don't currenty enable PSR except on the EDP transcoder. v2: From DK * Rebased on drm-tip Cc: Rodrigo Vivi Signed-off-by: Ville Syrjälä Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/i915_irq.c | 57 ++++++++++++++++++++++++++++-------- drivers/gpu/drm/i915/i915_reg.h | 7 +++-- drivers/gpu/drm/i915/intel_display.h | 4 +++ 3 files changed, 52 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index e94a835b7515..56228e8ed980 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2395,20 +2395,34 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, static void hsw_edp_psr_irq_handler(struct drm_i915_private *dev_priv) { u32 edp_psr_iir = I915_READ(EDP_PSR_IIR); + u32 edp_psr_imr = I915_READ(EDP_PSR_IMR); + u32 mask = BIT(TRANSCODER_EDP); + enum transcoder cpu_transcoder; - if (edp_psr_iir & EDP_PSR_ERROR) - DRM_DEBUG_KMS("PSR error\n"); - - if (edp_psr_iir & EDP_PSR_PRE_ENTRY) { - DRM_DEBUG_KMS("PSR prepare entry in 2 vblanks\n"); - I915_WRITE(EDP_PSR_IMR, EDP_PSR_PRE_ENTRY); - } + if (INTEL_GEN(dev_priv) >= 8) + mask |= BIT(TRANSCODER_A) | + BIT(TRANSCODER_B) | + BIT(TRANSCODER_C); + + for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, mask) { + if (edp_psr_iir & EDP_PSR_ERROR(cpu_transcoder)) + DRM_DEBUG_KMS("Transcoder %s PSR error\n", + transcoder_name(cpu_transcoder)); + + if (edp_psr_iir & EDP_PSR_PRE_ENTRY(cpu_transcoder)) { + DRM_DEBUG_KMS("Transcoder %s PSR prepare entry in 2 vblanks\n", + transcoder_name(cpu_transcoder)); + edp_psr_imr |= EDP_PSR_PRE_ENTRY(cpu_transcoder); + } - if (edp_psr_iir & EDP_PSR_POST_EXIT) { - DRM_DEBUG_KMS("PSR exit completed\n"); - I915_WRITE(EDP_PSR_IMR, 0); + if (edp_psr_iir & EDP_PSR_POST_EXIT(cpu_transcoder)) { + DRM_DEBUG_KMS("Transcoder %s PSR exit completed\n", + transcoder_name(cpu_transcoder)); + edp_psr_imr &= ~EDP_PSR_PRE_ENTRY(cpu_transcoder); + } } + I915_WRITE(EDP_PSR_IMR, edp_psr_imr); I915_WRITE(EDP_PSR_IIR, edp_psr_iir); } @@ -2556,11 +2570,22 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) if (master_ctl & GEN8_DE_MISC_IRQ) { iir = I915_READ(GEN8_DE_MISC_IIR); if (iir) { + bool found = false; + I915_WRITE(GEN8_DE_MISC_IIR, iir); ret = IRQ_HANDLED; - if (iir & GEN8_DE_MISC_GSE) + + if (iir & GEN8_DE_MISC_GSE) { intel_opregion_asle_intr(dev_priv); - else + found = true; + } + + if (iir & GEN8_DE_EDP_PSR) { + hsw_edp_psr_irq_handler(dev_priv); + found = true; + } + + if (!found) DRM_ERROR("Unexpected DE Misc interrupt\n"); } else @@ -3318,6 +3343,9 @@ static void gen8_irq_reset(struct drm_device *dev) gen8_gt_irq_reset(dev_priv); + I915_WRITE(EDP_PSR_IMR, 0xffffffff); + I915_WRITE(EDP_PSR_IIR, 0xffffffff); + for_each_pipe(dev_priv, pipe) if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) @@ -3807,7 +3835,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) uint32_t de_pipe_enables; u32 de_port_masked = GEN8_AUX_CHANNEL_A; u32 de_port_enables; - u32 de_misc_masked = GEN8_DE_MISC_GSE; + u32 de_misc_masked = GEN8_DE_MISC_GSE | GEN8_DE_EDP_PSR; enum pipe pipe; if (INTEL_GEN(dev_priv) >= 9) { @@ -3832,6 +3860,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) else if (IS_BROADWELL(dev_priv)) de_port_enables |= GEN8_PORT_DP_A_HOTPLUG; + gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR); + I915_WRITE(EDP_PSR_IMR, 0); + for_each_pipe(dev_priv, pipe) { dev_priv->de_irq_mask[pipe] = ~de_pipe_masked; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3447f03eac3d..578a0ac74bfb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3831,9 +3831,9 @@ enum { /* Bspec claims those aren't shifted but stay at 0x64800 */ #define EDP_PSR_IMR _MMIO(0x64834) #define EDP_PSR_IIR _MMIO(0x64838) -#define EDP_PSR_ERROR (1<<2) -#define EDP_PSR_POST_EXIT (1<<1) -#define EDP_PSR_PRE_ENTRY (1<<0) +#define EDP_PSR_ERROR(trans) (1 << (((trans) * 8 + 10) & 31)) +#define EDP_PSR_POST_EXIT(trans) (1 << (((trans) * 8 + 9) & 31)) +#define EDP_PSR_PRE_ENTRY(trans) (1 << (((trans) * 8 + 8) & 31)) #define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10) #define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */ @@ -6760,6 +6760,7 @@ enum { #define GEN8_DE_MISC_IIR _MMIO(0x44468) #define GEN8_DE_MISC_IER _MMIO(0x4446c) #define GEN8_DE_MISC_GSE (1 << 27) +#define GEN8_DE_EDP_PSR (1 << 19) #define GEN8_PCU_ISR _MMIO(0x444e0) #define GEN8_PCU_IMR _MMIO(0x444e4) diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h index 4e7418b345bc..2ef31617614a 100644 --- a/drivers/gpu/drm/i915/intel_display.h +++ b/drivers/gpu/drm/i915/intel_display.h @@ -218,6 +218,10 @@ struct intel_link_m_n { for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \ for_each_if((__mask) & BIT(__p)) +#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ + for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \ + for_each_if ((__mask) & (1 << (__t))) + #define for_each_universal_plane(__dev_priv, __pipe, __p) \ for ((__p) = 0; \ (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \