diff mbox series

[05/10] drm/i915/icl: Trim down posting reads on master intr control

Message ID 20180920143350.29249-6-mika.kuoppala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series ICL interrupt handling improvements | expand

Commit Message

Mika Kuoppala Sept. 20, 2018, 2:33 p.m. UTC 
If we return a master control value on disable, it will act
as a posting read and further streamline our interrupt handler.
We can then safely use the inlined helpers on irq reset
and on postinstall. Posting read on postinstall is
superfluous as nothing beneath it is depedent.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

Comments

Chris Wilson Sept. 20, 2018, 2:58 p.m. UTC | #1 
Quoting Mika Kuoppala (2018-09-20 15:33:45)
> If we return a master control value on disable, it will act
> as a posting read and further streamline our interrupt handler.
> We can then safely use the inlined helpers on irq reset
> and on postinstall. Posting read on postinstall is
> superfluous as nothing beneath it is depedent.
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

Ok, this adds more weight to patch 4. The question about extending the
pattern back as far as it goes still applies :)

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 89d76e7f4d00..c35576f9c3f5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3125,9 +3125,11 @@  static inline void gen11_master_irq_enable(void __iomem * const regs)
 	raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
 }
 
-static inline void gen11_master_irq_disable(void __iomem * const regs)
+static inline u32 gen11_master_irq_disable(void __iomem * const regs)
 {
 	raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
+
+	return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ;
 }
 
 static irqreturn_t gen11_irq_handler(int irq, void *arg)
@@ -3140,8 +3142,7 @@  static irqreturn_t gen11_irq_handler(int irq, void *arg)
 	if (!intel_irqs_enabled(i915))
 		return IRQ_NONE;
 
-	gen11_master_irq_disable(regs);
-	master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ;
+	master_ctl = gen11_master_irq_disable(regs);
 
 	/* Find, clear, then process each source of interrupt. */
 	gen11_gt_irq_handler(i915, master_ctl);
@@ -3652,10 +3653,10 @@  static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
 static void gen11_irq_reset(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	void __iomem * const regs = dev_priv->regs;
 	int pipe;
 
-	I915_WRITE(GEN11_GFX_MSTR_IRQ, 0);
-	POSTING_READ(GEN11_GFX_MSTR_IRQ);
+	gen11_master_irq_disable(regs);
 
 	gen11_gt_irq_reset(dev_priv);
 
@@ -4308,6 +4309,7 @@  static void icp_irq_postinstall(struct drm_device *dev)
 static int gen11_irq_postinstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	void __iomem * const regs = dev_priv->regs;
 	u32 gu_misc_masked = GEN11_GU_MISC_GSE;
 
 	if (HAS_PCH_ICP(dev_priv))
@@ -4320,8 +4322,7 @@  static int gen11_irq_postinstall(struct drm_device *dev)
 
 	I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
 
-	I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
-	POSTING_READ(GEN11_GFX_MSTR_IRQ);
+	gen11_master_irq_enable(regs);
 
 	return 0;
 }