From patchwork Thu Sep 20 14:33:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 10607845 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8F0D21508 for ; Thu, 20 Sep 2018 14:34:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7EB5C2D9C4 for ; Thu, 20 Sep 2018 14:34:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 735932D9E0; Thu, 20 Sep 2018 14:34:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 22A9B2D9E1 for ; Thu, 20 Sep 2018 14:34:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8D86D6E60B; Thu, 20 Sep 2018 14:34:24 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3CAF06E60F for ; Thu, 20 Sep 2018 14:34:13 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Sep 2018 07:34:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,398,1531810800"; d="scan'208";a="93422378" Received: from rosetta.fi.intel.com ([10.237.72.186]) by orsmga002.jf.intel.com with ESMTP; 20 Sep 2018 07:34:10 -0700 Received: by rosetta.fi.intel.com (Postfix, from userid 1000) id 0D28B840851; Thu, 20 Sep 2018 17:33:52 +0300 (EEST) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Thu, 20 Sep 2018 17:33:47 +0300 Message-Id: <20180920143350.29249-8-mika.kuoppala@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180920143350.29249-1-mika.kuoppala@linux.intel.com> References: <20180920143350.29249-1-mika.kuoppala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 07/10] drm/i915/icl: Make own function for display irq handler X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Move display interrupt handling outside of generic handler. Cc: Chris Wilson Cc: Ville Syrjälä Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_irq.c | 36 ++++++++++++++++++++------------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index e9034d6d87b0..506cfd048dd6 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3118,6 +3118,27 @@ gen11_gu_misc_irq_handler(struct drm_i915_private *dev_priv, DRM_ERROR("Unexpected GU_MISC interrupt 0x%x\n", iir); } +static void +gen11_display_irq_handler(struct drm_i915_private * const i915, + const u32 master_ctl) +{ + u32 disp_ctl; + + if (!(master_ctl & GEN11_DISPLAY_IRQ)) + return; + + /* IRQs are synced during runtime_suspend, we don't require a wakeref */ + disp_ctl = raw_reg_read(i915->regs, GEN11_DISPLAY_INT_CTL); + + disable_rpm_wakeref_asserts(i915); + /* + * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ + * for the display related bits. + */ + gen8_de_irq_handler(i915, disp_ctl); + enable_rpm_wakeref_asserts(i915); +} + static inline void gen11_master_irq_enable(void __iomem * const regs) { raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ); @@ -3144,20 +3165,7 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg) /* Find, clear, then process each source of interrupt. */ gen11_gt_irq_handler(i915, master_ctl); - - /* IRQs are synced during runtime_suspend, we don't require a wakeref */ - if (master_ctl & GEN11_DISPLAY_IRQ) { - const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL); - - disable_rpm_wakeref_asserts(i915); - /* - * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ - * for the display related bits. - */ - gen8_de_irq_handler(i915, disp_ctl); - enable_rpm_wakeref_asserts(i915); - } - + gen11_display_irq_handler(i915, master_ctl); gu_misc_iir = gen11_gu_misc_irq_ack(regs, master_ctl); gen11_master_irq_enable(regs);