diff mbox series

[2/2] drm/i915/gen9: WaRsDoubleRc6WrlWithCoarsePowerGating is for all gen9

Message ID 20180924114819.12637-2-mika.kuoppala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series [1/2] drm/i915/gen9: WaRsClearFWBitsAtFLR is for all gen9 | expand

Commit Message

Mika Kuoppala Sept. 24, 2018, 11:48 a.m. UTC 
We used to enable this for skl only, but it is for all gen9.

Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
Cc: Akash Goel <akash.goel@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Alex Dai <yu.dai@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1db9b8328275..330bbd41eff1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6899,10 +6899,10 @@  static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
 	if (INTEL_GEN(dev_priv) >= 10) {
 		I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
 		I915_WRITE(GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
-	} else if (IS_SKYLAKE(dev_priv)) {
+	} else if (IS_GEN9(dev_priv)) {
 		/*
-		 * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
-		 * when CPG is enabled
+		 * WaRsDoubleRc6WrlWithCoarsePowerGating:skl,bxt,kbl,glk,cfl
+		 * Doubling WRL only when CPG is enabled
 		 */
 		I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
 	} else {