From patchwork Fri Sep 28 16:47:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 10620191 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 36C376CB for ; Fri, 28 Sep 2018 16:49:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 349A62BF23 for ; Fri, 28 Sep 2018 16:49:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2855F2BE58; Fri, 28 Sep 2018 16:49:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DDB312BF23 for ; Fri, 28 Sep 2018 16:49:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 36FA36E683; Fri, 28 Sep 2018 16:49:43 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9BC3A6E23B for ; Fri, 28 Sep 2018 16:49:41 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Sep 2018 09:49:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,315,1534834800"; d="scan'208";a="76909701" Received: from invictus.jf.intel.com ([10.54.75.152]) by orsmga007.jf.intel.com with ESMTP; 28 Sep 2018 09:46:21 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Fri, 28 Sep 2018 09:47:38 -0700 Message-Id: <20180928164738.9756-7-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20180928164738.9756-1-radhakrishna.sripada@intel.com> References: <20180928164738.9756-1-radhakrishna.sripada@intel.com> Subject: [Intel-gfx] [PATCH 7/7] drm/i915/icl: Add Wa_1406609255 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Shader feature to prefetch binding tables does not support 16:6 18:8 BTP formats. Enabling fault handling could result in hangs with faults. Disabling demand prefetch would disable binding table prefetch. Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4b472bc2d26d..117ae5bf647c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7411,6 +7411,9 @@ enum { #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11) +#define GEN7_SARCHKMD _MMIO(0xB000) +#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31) + #define GEN7_L3SQCREG1 _MMIO(0xB010) #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index 54a63c9b694f..9d5f48b98803 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -909,6 +909,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv) /* WaEnable32PlaneMode:icl */ I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE)); + + /* Wa_1406609255:icl (pre-prod) */ + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_C0)) + I915_WRITE(GEN7_SARCHKMD, + I915_READ(GEN7_SARCHKMD) | + GEN7_DISABLE_DEMAND_PREFETCH); } void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)