From patchwork Mon Oct 1 15:26:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10622331 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C66A91515 for ; Mon, 1 Oct 2018 15:26:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BAC5A29604 for ; Mon, 1 Oct 2018 15:26:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AE3992963A; Mon, 1 Oct 2018 15:26:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 506E629604 for ; Mon, 1 Oct 2018 15:26:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8014A89E5B; Mon, 1 Oct 2018 15:26:56 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) by gabe.freedesktop.org (Postfix) with ESMTPS id C64C589E5B for ; Mon, 1 Oct 2018 15:26:54 +0000 (UTC) Received: by mail-wm1-x343.google.com with SMTP id y140-v6so2848895wmd.0 for ; Mon, 01 Oct 2018 08:26:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sZN2pF47MPudczrFc8C5ZDlTEiinWsWbowKAKe+a0Bg=; b=sF/GxmXwaePJ6bJr1gokc//IAjfylklAs1ZBM+Mnjm9sAJAdy8avMxQW+pOkPUFcoq YakC02h/d5VUMW23+QOGgYynESwuBq82OQ9WfMzYeQwtN/PgAqTjWpT5pDyOE79ohQD2 t2pteBov3Gfx7wR1H121tI8L3TegQ/pwHs68gT+WkAejWtb7Tga+tii24AE6FubNrp6c 2g3cVx4ShuarXPnQu3hvuNxXGA2q01L1qf+t5VqoLn6PajL+tUrDDd9vbD0e46CVUltE xNhWNKfii30r4/J3MXwFfYOiomZQs2g/1Q/qGM0sp27KX4U+HVynb89OEW7QKB/1xa78 6lCw== X-Gm-Message-State: ABuFfoiYK5T+Fg2n5CjzTcZPSliwWn6nGB1NezkeVJFgyzVAHnmTMXaX yqbRBBksN0S6fDtsyoayM4EV7nGfBII= X-Google-Smtp-Source: ACcGV62LFRrmqn90R7VBuVXzC6SfwYZxA6m4epL3zsoSe5yILWbv2C2h11GpC07th3uD8MspHgHu2Q== X-Received: by 2002:a1c:ae84:: with SMTP id x126-v6mr9039671wme.73.1538407613001; Mon, 01 Oct 2018 08:26:53 -0700 (PDT) Received: from localhost.localdomain ([95.144.165.37]) by smtp.gmail.com with ESMTPSA id j9-v6sm11638654wrt.32.2018.10.01.08.26.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 01 Oct 2018 08:26:52 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Mon, 1 Oct 2018 16:26:47 +0100 Message-Id: <20181001152647.2105-1-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <395ddfac-3c5e-0559-d552-91cf36cd1d1f@intel.com> References: <395ddfac-3c5e-0559-d552-91cf36cd1d1f@intel.com> Subject: [Intel-gfx] [PATCH v3] drm/i915/icl: Support co-existence between per-context SSEU and OA X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin When OA is active we want to lock the powergating configuration, but on Icelake, users like the media stack will have issues if we lock to the full device configuration. Instead lock to a subset of (sub)slices which are currently a known working configuration for all users. v2: * Fix commit message spelling. v3: Lionel: * Add bspec reference. * Fix spelling in comment. Signed-off-by: Tvrtko Ursulin Bspec: 21140 Cc: Lionel Landwerlin Reviewed-by: Lionel Landwerlin --- drivers/gpu/drm/i915/intel_lrc.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index c6c5938684cf..2e8151192fc4 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -2577,13 +2577,28 @@ u32 gen8_make_rpcs(struct drm_i915_private *i915, struct intel_sseu *req_sseu) /* * If i915/perf is active, we want a stable powergating configuration - * on the system. The most natural configuration to take in that case - * is the default (i.e maximum the hardware can do). + * on the system. + * + * We could choose full enablement, but on ICL we know there are use + * cases which disable slices for functional, apart for performance + * reasons. So in this case we select a known stable subset. */ - if (unlikely(i915->perf.oa.exclusive_stream)) - ctx_sseu = intel_device_default_sseu(i915); - else + if (!i915->perf.oa.exclusive_stream) { ctx_sseu = *req_sseu; + } else { + ctx_sseu = intel_device_default_sseu(i915); + + if (IS_GEN11(i915)) { + /* + * We only need subslice count so it doesn't matter + * which ones we select - just turn off low bits in the + * amount of half of all available subslices per slice. + */ + ctx_sseu.subslice_mask = + ~(~0 << (hweight8(ctx_sseu.subslice_mask) / 2)); + ctx_sseu.slice_mask = 0x1; + } + } slices = hweight8(ctx_sseu.slice_mask); subslices = hweight8(ctx_sseu.subslice_mask);